Semiconductor Testing Apparatus and Method

Abstract

The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.

1 . A semiconductor testing apparatus for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising:
 function test execution unit for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference; and   power supply control unit for controlling the supply of power in such a manner that after the completion of execution of the function test execution unit, the supply thereof from the mounting portion to the device is stopped and the power is supplied again after a predetermined time,   wherein the function test execution unit performs at least one the function test, based on the function test execution unit after the resupply of power by the power supply control unit thereby to determine whether the operation of the reference cell is good.   
     
     
         2 . The semiconductor testing apparatus according to  claim 1 , wherein the normal cells are classified into plural sets and one said reference cell is provided for each set, and the function test execution unit performs a function test on the corresponding cell for every set. 
     
     
         3 . A semiconductor testing apparatus for mounting a device having a plurality of normal cells each including a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising:
 contact test execution unit for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all of the pads or terminals;   dc test execution unit for performing a dc test for inspecting a state of a direct current characteristic at an input/output of the device on all the cells;   function test execution unit for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference; and   power supply control unit for controlling the supply of power in such a manner that after the completion of execution of the contact test execution unit, the dc test execution unit and the function test execution unit, the supply thereof from the mounting portion to the device is stopped and the power is supplied again after a predetermined time,   wherein the function test execution unit performs at least one said function test, based on the function test execution unit after the resupply of power by the power supply control unit thereby to determine whether the operation of the reference cell is good.   
     
     
         4 . The semiconductor testing apparatus according to  claim 3 , wherein the normal cells are classified into plural sets and one said reference cell is provided for each set, and the function test execution unit performs a function test on the corresponding cell for every set. 
     
     
         5 . The semiconductor testing apparatus according to  claim 3 , wherein the contact test execution unit is executed after the elapse of the predetermined time and before the resupply of the power. 
     
     
         6 . The semiconductor testing apparatus according to  claim 4 , wherein the contact test execution unit is executed after the elapse of the predetermined time and before the resupply of the power. 
     
     
         7 . A semiconductor testing apparatus for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising:
 function test execution unit for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference,   wherein the function test execution unit preferentially performs a decision as to whether the operation of the reference cell is good, by conducting at least one said function test.