Printed circuit board with embedded chip capacitor and chip capacitor embedment method

Abstract

A printed circuit board having an embedded chip capacitor is disclosed. According to an embodiment of the present invention, a printed circuit board having an embedded chip capacitor can include a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, placed between the first conductive layer and the second conductive layer and having a second electrode, connected to the second conductive layer; and a via, connecting the first conductive layer to a first electrode of the chip capacitor. With the present invention, a problem mixed signals can be solved in the printed circuit board including an analog circuit and a digital circuit board by using the chip capacitor embedded in the printed circuit board as an electromagnetic bandgap structure. Here, various electrical devices or elements are mounted in the printed circuit board.

1 . A printed circuit board having an embedded chip capacitor, the printed circuit board comprising:
 a first conductive layer;   a second conductive layer, placed away from the first conductive layer;   a chip capacitor, placed between the first conductive layer and the second conductive layer and having a second electrode, connected to the second conductive layer; and   a via, connecting the first conductive layer to a first electrode of the chip capacitor.   
   
   
       2 . The printed circuit board of  claim 1 , wherein a via land is formed in one end part of the via, and
 the via is connected to the first electrode through the via land formed in the one end part of the via, and the other end part of the via is connected to the first conductive layer.   
   
   
       3 . The printed circuit board of  claim 2 , wherein the chip capacitor comprises a first electrode, a dielectric member, placed on the first electrode, and a second electrode, placed on the dielectric member,
 whereas the chip capacitor is seated on the via land.   
   
   
       4 . The printed circuit board of  claim 2 , wherein the chip capacitor comprises a dielectric member, a first electrode, which is coupled to a right side of the dielectric member, and a second electrode, which is coupled to a left side of the dielectric member,
 whereas a clearance hole is formed in a part corresponding to a position of the first electrode in the second conductive layer to allow the first electrode to be electrically disconnected to the second conductive layer.   
   
   
       5 . The printed circuit board of  claim 1 , wherein any one of the first conductive layer and the second conductive layer is a power layer, and the other end part is a ground part. 
   
   
       6 . The printed circuit board of  claim 1 , wherein an etched pattern is formed in an open-curved line shape in a surrounding area of a part corresponding to a position of the via or the chip capacitor in the first conductive layer or the second conductive layer. 
   
   
       7 . The printed circuit board of  claim 6 , wherein the etched pattern has a spiral shape. 
   
   
       8 . The printed circuit board of  claim 1 , wherein the chip capacitor is coupled to an inductance component by the via, connected to the chip capacitor in series, to intercept the transfer of an electromagnetic wave having a desired frequency band. 
   
   
       9 . The printed circuit board of  claim 1 , wherein a plurality of series connection structures between the chip capacitor and the via are arranged in a noise transferable path between a noise source and a noise prevented destination. 
   
   
       10 . The printed circuit board of  claim 9 , wherein the printed circuit board is mounted with a digital circuit and an analog circuit, and
 the noise source and the noise prevented destination correspond to one and the other, respectively, of positions in which the digital circuit and the analog circuit are supposed to be mounted in the printed circuit board.   
   
   
       11 . The printed circuit board of  claim 9 , wherein the series connection structure between the chip capacitor and the via is arranged in a band structure in the noise transferable path. 
   
   
       12 . The printed circuit board of  claim 11 , wherein the band structure has a shape enveloping at least one of the noise source and the noise prevented destination. 
   
   
       13 . The printed circuit board of  claim 12 , wherein the band structure has any one of a closed loop shape, a rectangular shape with one side open, and an ‘L’ shape. 
   
   
       14 . The printed circuit board of  claim 11 , wherein the band structure has a straight-line shape of at least one line to separate the noise source and the noise prevented destination by crossing the area between the noise source and the noise prevented destination. 
   
   
       15 . A printed circuit board having an embedded chip capacitor, the printed circuit board comprising:
 a first conductive layer;   a second conductive layer, placed away from the first conductive layer;   a chip capacitor, having a first electrode connected to the first conductive layer through being seated in a cavity formed between the first conductive layer and the second conductive layer;   a filled material, filled in a space excluding the space occupied by the chip capacitor in the cavity; and   a via, penetrating the filled material and connecting the second conductive layer to the second electrode of the chip capacitor.   
   
   
       16 . The printed circuit board of  claim 15 , wherein any one of the first conductive layer and the second conductive layer is a power layer, and the other end part is a ground part. 
   
   
       17 . The printed circuit board of  claim 15 , wherein an etched pattern is formed in an open-curved line shape in a surrounding area of a part corresponding to a position of the via or the chip capacitor in the first conductive layer or the second conductive layer. 
   
   
       18 . The printed circuit board of  claim 17 , wherein the etched pattern has a spiral shape. 
   
   
       19 . The printed circuit board of  claim 15 , wherein the chip capacitor is coupled to an inductance component by the via, connected to the chip capacitor in series, to intercept the transfer of an electromagnetic wave having a desired frequency band. 
   
   
       20 . The printed circuit board of  claim 15 , wherein a plurality of series connection structures between the chip capacitor and the via are arranged in a noise transferable path between a noise source and a noise prevented destination. 
   
   
       21 . The printed circuit board of  claim 20 , wherein the printed circuit board is mounted with a digital circuit and an analog circuit, and
 the noise source and the noise prevented destination correspond to one and the other, respectively, of positions in which the digital circuit and the analog circuit are supposed to be mounted in the printed circuit board.   
   
   
       22 . The printed circuit board of  claim 20 , wherein the series connection structure between the chip capacitor and the via is arranged in a band structure in the noise transferable path. 
   
   
       23 . The printed circuit board of  claim 22 , wherein the band structure has a shape enveloping at least one of the noise source and the noise prevented destination. 
   
   
       24 . The printed circuit board of  claim 23 , wherein the band structure has any one of a closed loop shape, a rectangular shape with one side open, and an ‘L’ shape. 
   
   
       25 . The printed circuit board of  claim 22 , wherein the band structure has a straight-line shape of at least one line to separate the noise source and the noise prevented destination by crossing the area between the noise source and the noise prevented destination. 
   
   
       26 . A method of embedding a chip capacitor in a printed circuit board including a first conductive layer and a dielectric layer placed on the first conductive layer, the method comprising:
 removing the dielectric layer to form a cavity exposing the first conductive layer;   seating a chip capacitor in the cavity;   filling a filled material at a space excluding the space occupied by the chip capacitor in the cavity;   forming a via penetrating the filled material and being connected to the chip capacitor; and   stacking a conductive material to constitute a second conductive layer in surfaces of the via and the dielectric layer and in an surface of the filled material filled in the cavity.   
   
   
       27 . The method of  claim 26 , wherein the chip capacitor comprises a first electrode, a dielectric member, placed on the first electrode, and a second electrode, placed on the dielectric member, and
 the first electrode is connected to the first conductive layer, and the second electrode is connected to the second conductive layer through the via.   
   
   
       28 . The method of  claim 26 , further comprising: forming an etched pattern in an open-curved line shape in a surrounding area of a part corresponding to a position in which the cavity is supposed to be formed in the first conductive layer. 
   
   
       29 . The method of  claim 26 , wherein the etched pattern has a spiral shape. 
   
   
       30 . The method of  claim 26 , further comprising: forming an etched pattern in an open-curved line shape in a surrounding area of a part corresponding to a position in which the via is formed in the second conductive layer. 
   
   
       31 . The method of  claim 26 , wherein the etched pattern has a spiral shape.