Semiconductor device reducing leakage current of transistor

Abstract

A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electrode coupled to the input node, a first conductive electrode coupled to the output node, and a second conductive electrode coupled to a power supply node; and a first switch element connected between the power supply node and the second conductive electrode of the second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of the clock.

1 . A semiconductor device comprising:
 a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode;   a second transistor having a control electrode coupled to said input node, a first conductive electrode coupled to said output node, and a second conductive electrode coupled to a power supply node; and   a first switch element connected between said power supply node and said second conductive electrode of said second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of said clock.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a third transistor having a control electrode coupled to said input node, a first conductive electrode coupled to said output node, and a second conductive electrode coupled to a power supply node; and   a second switch element connected between said power supply node and said second conductive electrode of said third transistor and turned on and off based on a second control signal indicating a detection result of a frequency of said clock.   
     
     
         3 . A semiconductor device comprising:
 a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; and   a second transistor having a control electrode coupled to said input node, a first conductive electrode coupled to said output node, a second conductive electrode, and a back gate at which a potential is changed based on a control signal indicating a detection result of a frequency of said clock.   
     
     
         4 . A semiconductor device comprising:
 a first transistor having a control electrode coupled to an input node, a first conductive electrode coupled to an output node and a first power supply line, and a second conductive electrode coupled to a second power supply line; and   second to fourth transistors each having a control electrode coupled to said input node, a first conductive electrode coupled to said output node and said first power supply line, and a second conductive electrode coupled to a third power supply line to which electric power supply is controlled between on and off, wherein   said second power supply line, said first power supply line and said third power supply line are arranged in this order while being spaced away from one another,   said first transistor and said second transistor are arranged side by side between said first power supply line and said second power supply line in an extending direction of said first power supply line and said second power supply line, and   said third transistor and said fourth transistor are arranged side by side between said first power supply line and said third power supply line in the extending direction of said first power supply line and said third power supply line.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein
 a plurality of regions each including said first to third power supply lines and said first to fourth transistors are arranged in an arranging direction of said first to third power supply lines, and   said adjoining regions are arranged so as to be symmetrical with each other, and share one of said second power supply line and said third power supply line.   
     
     
         6 . The semiconductor device according to  claim 4 , wherein
 each of said first to fourth transistors is of a first conduction type,   said semiconductor device further comprising:   second conduction type fifth to eighth transistors each having a control electrode coupled to said input node,   said fifth to eighth transistors being connected between said first conductive electrode of each of said first to fourth transistors and said first power supply line and being substantially equal in size to said first transistor, wherein   said fifth transistor and said sixth transistor are arranged side by side between each of said first and second transistors and said first power supply line in the extending direction of said first power supply line and said second power supply line, and   said seventh transistor and said eighth transistor are arranged side by side between each of said third and fourth transistors and said first power supply line in the extending direction of said first power supply line and said third power supply line.   
     
     
         7 . A semiconductor device comprising:
 a first conduction type first transistor having a control electrode coupled to an input node, a first conductive electrode coupled to an output node, and a second conductive electrode coupled to a second power supply line;   first conduction type second to fourth transistors each having a control electrode coupled to said input node, a first conductive electrode coupled to said output node, and a second conductive electrode coupled to a third power supply line to which electric power supply is controlled between on and off; and   second conduction type fifth to eighth transistors each having a control electrode coupled to said input node, a first conductive electrode coupled to said output node, and a second conductive electrode coupled to a first power supply line, wherein   said first to eighth transistors are substantially equal in size to one another,   said second power supply line, said first power supply line and said third power supply line are arranged in this order while being spaced away from one another,   said first transistor and said seventh transistor are arranged side by side between said first power supply line and said second power supply line in an extending direction of said first power supply line and said second power supply line,   said second transistor and said fourth transistor are arranged side by side between said first power supply line and said third power supply line in the extending direction of said first power supply line and said third power supply line,   said fifth transistor and said eighth transistor are arranged side by side between each of said first and seventh transistors and said first power supply line in the extending direction of said first power supply line and said second power supply line, and   said sixth transistor and said third transistor are arranged side by side between each of said second and fourth transistors and said first power supply line in the extending direction of said first power supply line and said third power supply line.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein
 a plurality of regions each including said first to third power supply lines and said first to eighth transistors are arranged in an arranging direction of said first to third power supply lines, and   said adjoining regions are arranged so as to be symmetrical with each other, and share one of said second power supply line and said third power supply line.   
     
     
         9 . A semiconductor device comprising:
 a first transistor having a control electrode coupled to an input node, a first conductive electrode coupled to an output node and a first power supply line, and a second conductive electrode coupled to a second power supply line; and   second to fourth transistors each having a control electrode coupled to said input node, a first conductive electrode coupled to said output node and said first power supply line, a second conductive electrode coupled to said second power supply line, and a well corresponding to a back gate and having a changeable potential,   said second to fourth transistors being substantially equal in size to said first transistor, wherein   said first power supply line and said second power supply line are arranged while being spaced away from each other,   said first transistor and said second transistor are arranged side by side between said first power supply line and said second power supply line in an extending direction of said first power supply line and said second power supply line, and   said third transistor and said fourth transistor are arranged side by side in the extending direction of said first power supply line and said second power supply line on a side opposite to said first transistor and said second transistor with respect to said first power supply line.   
     
     
         10 . The semiconductor device according to  claim 9 , wherein
 said well of each of said third and fourth transistors is coupled to a back gate power supply line to which a changeable voltage is supplied,   a plurality of regions each including said first and second power supply lines and said first to fourth transistors are arranged in an arranging direction of said first power supply line and said second power supply line,   said well of said second transistor in one of said adjoining regions is coupled to at least any one of said well of said third transistor and said well of said fourth transistor in the other one of said adjoining regions.   
     
     
         11 . The semiconductor device according to  claim 9 , wherein
 said back gate power supply line is arranged so as to extend in the arranging direction of said first power supply line and said second power supply line.   
     
     
         12 . The semiconductor device according to  claim 9 , wherein
 each of said first to fourth transistors is of a first conduction type,   said semiconductor device further comprising:   a second conduction type fifth transistor having a control electrode coupled to said input node,   said fifth transistor being connected between said first conductive electrode of said first transistor and said first power supply line and being substantially equal in size to said first transistor; and   second conduction type sixth to eighth transistors each having a control electrode coupled to said input node, and a well corresponding to a back gate and having a changeable potential,   said sixth to eighth transistors being connected between said first conductive electrode of each of said second to fourth transistors and said first power supply line and being substantially equal in size to said first transistor, wherein   said fifth transistor and said sixth transistor are arranged side by side between each of said first and second transistors and said first power supply line in the extending direction of said first power supply line and said second power supply line, and   said seventh transistor and said eighth transistor are arranged side by side between each of said third and fourth transistors and said first power supply line in the extending direction of said first power supply line and said second power supply line.