Semiconductor integrated circuit and method for controlling semiconductor integrated circuit

Abstract

When a master circuit is in an inactive state, a slave circuit assigned to the master circuit is not used. Accordingly, the use efficiency of system recourses is decreased. To solve the above problem, a semiconductor integrated circuit reassigns a M2 region of a slave circuit, previously assigned to a first master circuit, to a second master circuit. That is to say, the M2 region of the slave circuit previously assigned to the first master circuit is reassigned to the second master circuit based on the operational status of the first master circuit. This improves the use efficiency of system resources of the semiconductor integrated circuit.

1 . A semiconductor integrated circuit, comprising:
 a first master circuit;   a second master circuit; and   a first slave circuit being assigned to said first master circuit, wherein   said first slave circuit is reassigned to said second master circuit based on an operational status of said first master circuit.   
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , further comprising
 a first bus coupled to at least said first master circuit, said first slave circuit and said second master circuit, wherein   said first slave circuit is reassigned to said second master circuit by changing settings of said first bus.   
     
     
         3 . The semiconductor integrated circuit according to  claim 2 , wherein
 a master identifier transmitted to said first slave circuit via said first bus after changing said settings of said first bus is equal to a master identifier pre-set in said first master circuit.   
     
     
         4 . The semiconductor integrated circuit according to  claim 2 , further comprising
 a system controller that changes said settings of said first bus.   
     
     
         5 . The semiconductor integrated circuit according to  claim 4 , further comprising
 a bus controller coupled to said first bus, wherein   said system controller changes settings of said first bus by changing a hold value stored in a register included in said bus controller.   
     
     
         6 . The semiconductor integrated circuit according to  claim 4 , further comprising
 a master status register that holds a state value indicating the operation status of at least said first master circuit, wherein   said system controller changes settings of said first bus when said state value indicates that said first master circuit is in an inactive state.   
     
     
         7 . The semiconductor integrated circuit according to  claim 4 , wherein
 said system controller controls stop-start of at least said first master circuit and said second master circuit.   
     
     
         8 . The semiconductor integrated circuit according to  claim 6 , wherein
 said system controller starts said second master circuit when said state value in said master status register indicates that said first master circuit is in an inactive state.   
     
     
         9 . The semiconductor integrated circuit according to  claim 4 , wherein
 said system controller is coupled to an interface circuit of said second master circuit via said first bus.   
     
     
         10 . The semiconductor integrated circuit according to  claim 4 , further comprising
 a third master circuit having an interface circuit to which the system controller is coupled, wherein   said system controller changes said settings of said first bus by utilizing said third master circuit.   
     
     
         11 . The semiconductor integrated circuit according to  claim 10 , wherein
 the system controller is coupled to said interface circuit of said third master circuit via an external terminal.   
     
     
         12 . The semiconductor integrated circuit according to  claim 1 , further comprising
 a second bus coupled to said first master circuit and said second master circuit.   
     
     
         13 . The semiconductor integrated circuit according to  claim 12 , further comprising
 a third bus coupled to said second master circuit and said first slave circuit.   
     
     
         14 . The semiconductor integrated circuit according to  claim 12 , further comprising
 a system controller that controls said settings of at least said second bus.   
     
     
         15 . The semiconductor integrated circuit according to  claim 14 , wherein
 said system controller changes settings of said second bus based on a change of a hold value in a mode control register coupled to said second bus.   
     
     
         16 . The semiconductor integrated circuit according to  claim 12 , wherein
 said first master circuit and said second master circuit are incorporated in a master module coupled to a first bus.   
     
     
         17 . The semiconductor integrated circuit according to  claim 16 , further comprising:
 a third master circuit; and   a second slave circuit that is assigned to said third master circuit, wherein   said third master circuit and said second slave circuit are further coupled to said first bus, and   said second slave circuit is reassigned to said master module based on said operational status of said third master circuit.   
     
     
         18 . A method for controlling a semiconductor integrated circuit including a first master circuit, a second master circuit and at least one slave circuit, the method comprising:
 upon detection that an operational status of said first master circuit is in an inactive state, reassigning said slave circuit, which is previously assigned to said first master circuit, to said second master circuit.   
     
     
         19 . The method for controlling a semiconductor integrated circuit according to  claim 18 , wherein
 said slave circuit is reassigned to said second master circuit based on a change of settings of a first bus coupled to at least said first master circuit, said slave circuit and said second master circuit.   
     
     
         20 . The method for controlling a semiconductor integrated circuit according to  claim 18 , wherein
 any one of said first master circuit and said second master circuit is enabled to access a first bus based on a change of settings of a second bus that is coupled to said first master circuit and said second master circuit.