Wafer level packaged mems device

Abstract

An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped.

1 . A wafer level packaged sensor device comprising:
 a base section formed of a silicon-on-insulator (SOI) wafer comprising:
 an active layer having one or more etched active components; 
 a handle layer; and 
 a dielectric layer located between the active layer and the handle layer; and 
   a cover plate having a handle layer and dielectric layer,   wherein the dielectric layer of the cover plate is etched to correspond with the one or more active components, the cover plate being bonded to the base, at least one of the base wafer handle layer or cover plate handle layer and corresponding dielectric layer having one or more etched pit features for exposing a portion of the surface of the active layer.   
   
   
       2 . The device of  claim 1 , further comprising metallization located on the exposed surface of the active layer, the metallization being in electric communication with one or more of the active components. 
   
   
       3 . The device of  claim 2 , further comprising at least one isolator flange formed by selectively etching the base section and the cover plate at an exterior edge of the device. 
   
   
       4 . A method for forming a wafer level package device, the method comprising:
 etching at least one active component in an active layer of a base silicon-on-insulator (SOI) wafer, the SOI wafer having a handle layer separated from the active layer by a dielectric layer;   etching the dielectric layer in the vicinity of the formed active component;   etching a dielectric layer of a cover plate wafer to form cavities to coincide with the at least one active components, the cover plate having a handle layer attached to the cover plate wafer dielectric layer,   etching at least one of the handle layers and corresponding dielectric layer to expose the surface of the active layer; and   forming a metallization on a portion of the exposed surface of the active layer.   
   
   
       5 . The method of  claim 4 , further comprising etching at least one isolator flange into the base wafer and the cover plate wafer at an exterior edge. 
   
   
       6 . A wafer level packaged sensor device comprising:
 a base section formed of a silicon-on-insulator (SOI) wafer comprising:
 an active layer having one or more etched active components; 
 a handle layer; and 
 a dielectric layer located between the active layer and the handle layer; and 
   a cover plate formed of a silicon-on-insulator (SOI) wafer comprising:
 an active layer; 
 a handle layer; and 
 a dielectric layer, 
   wherein the dielectric layer and the active layer of the cover plate include etched one or more cavities to correspond with the one or more active components, the cover plate being bonded to the base, at least one of the base wafer handle layer or cover plate handle layer and corresponding dielectric layer having one or more etched pit features for exposing a portion of the surface of the corresponding active layer.   
   
   
       7 . The device of  claim 6 , further comprising metallization located on the exposed surface, the metallization being in electric communication with one or more of the active components. 
   
   
       8 . The device of  claim 7 , further comprising at least one isolator flange formed by selectively etching the base section and the cover plate at an exterior edge of the device. 
   
   
       9 . The device of  claim 6 , wherein the active layer of the base section having a level of dopant for resisting an anisotropic etching process and one or more set backs formed into the handle layer of the base section near the active components, the one or more set backs being formed by an anisotropic etch. 
   
   
       10 . A method for forming a wafer level package device, the method comprising:
 forming at least one active component in an active layer of a base silicon-on-insulator (SOI) wafer;   applying a dopant to the active layer;   anisotropically etching a handle layer of the SOI wafer in the vicinity of the at least one active component;   etching an active layer and a dielectric layer of a cover plate SOI wafer to form one or more cavities to coincide with the active components of the base wafer;   bonding the SOI wafer to the cover plate SOI wafer;   etching at least one of the handle layers and corresponding dielectric layer to expose the surface of the corresponding active layer from the base SOI wafer or from the cover plate SOI wafer; and   forming a metallization on at least a portion of the exposed active layer.   
   
   
       11 . The method of  claim 10 , further comprising etching the SOI wafers in order to form one or more isolation flanges.