Solid state disk storage system with parallel accesssing architecture and solid state disck controller

Abstract

A solid state disk (SSD) storage system with a parallel accessing architecture, including a SSD controller and a plurality of transmission interfaces of a predetermined bit number and bandwidth, and a solid state disk controller thereof are provided. The SD controller forms channels for transmitting control signals and data with one or more flash memories through each of the transmission interfaces. That is, independent transmission channels are constituted between the SSD controller, the transmission interfaces with multiple bits, and the flash memories. In one embodiment, the transmission interfaces are compatible with MMC 4.0 protocol or higher. Moreover, a host controls and accesses the flash memories through a SATA bus interface and the SSD controller, and uses a direct memory access (DMA) engine with a bidirectional connection port in the SSD controller to transmit data.

1 . A solid state disk (SSD) storage system, comprising:
 a SSD controller, connected to an external host via a high-speed serial connection interface, and comprising a microprocessor, a direct memory access (DMA) engine, a buffer, and a host transmission interface, wherein the host transmission interface has a plurality of transmission interface host controllers, and the DMA engine is connected to the buffer, and is connected to the host via the high-speed serial connection interface;   a plurality of flash memory controllers, wherein each of the flash memory controllers is connected to corresponding one of the plurality of the transmission interface host controllers, and the flash memory controllers are connected to the transmission interface host controllers in parallel; and   a plurality of flash memories, wherein the flash memory controller is connected to at least two of the flash memories in parallel,   wherein a plurality of independent parallel transmission channels are established between the SSD controller and the flash memory controllers, and data transmission between the host and the flash memories is performed through the transmission channels under control of the DMA engine.   
   
   
       2 . The SSD storage system as claimed in  claim 1 , wherein the high-speed serial connection interface is a SATA connection interface. 
   
   
       3 . The SSD storage system as claimed in  claim 1 , wherein the high-speed serial connection interface is a PCI Express connection interface. 
   
   
       4 . The SSD storage system as claimed in  claim 1 , wherein the high-speed serial connection interface is a serial attached SCSI (SAS) connection interface. 
   
   
       5 . The SSD storage system as claimed in  claim 1 , wherein the SSD controller further comprises a memory arbitrator connected to the microprocessor and the host transmission interface, for arbitrating a priority sequence that the buffer to be accessed by the microprocessor or the host transmission interface. 
   
   
       6 . The SSD storage system as claimed in  claim 1 , wherein the host transmission interface is a MMC interface, the transmission interface host controller is a MMC host controller, and the flash memory controller is a MMC-flash memory controller. 
   
   
       7 . The SSD storage system as claimed in  claim 1 , wherein the host transmission interface is one of a SD card control interface or a CF card control interface. 
   
   
       8 . The SSD storage system as claimed in  claim 1 , wherein data transmission buses between the transmission interface host controllers and the flash memory controllers comprise 8-bit data buses, and 8-bit data buses are also arranged between the flash memory controllers and the flash memories connected in parallel. 
   
   
       9 . The SSD storage system as claimed in  claim 1 , wherein when the SSD controller receives an accessing request signal from the host, the microprocessor starts and sets the DMA engine, such that the DMA engine controls the data transmission between the host and the flash memories through the transmission channels. 
   
   
       10 . The SSD storage system as claimed in  claim 1 , wherein the flash memory controller further comprises a wear-leveling function, an error correction code (ECC) function, a garbage collection function, a bad block management (BBM) function or a combination thereof. 
   
   
       11 . The SSD storage system as claimed in  claim 1 , wherein a control signal and a data signal are included in buses connecting the flash memory controllers to the flash memories, the data signal has 8 bits, and the control signal comprises a command latch enable signal, an address latch enable signal, a write enable inversion signal, a write protect inversion signal, a complementary of chip enable signal, a read enable inversion signal, and a ready/busy inversion signal. 
   
   
       12 . A solid state disk (SSD) storage system, comprising:
 a SSD controller, connected to an external host via a high-speed serial connection interface, and comprising a microprocessor, a direct memory access (DMA) engine, a buffer, and a host transmission interface, wherein the host transmission interface has a plurality of transmission interface host controllers, and the DMA engine is connected to the buffer, and is connected to the host via the high-speed serial connection interface;   a plurality of flash memory controllers, wherein each of the flash memory controllers is connected to corresponding one of the transmission interface host controllers, and the flash memory controllers are connected to the transmission interface host controllers in parallel; and   a flash memory array, comprising a plurality of rows of flash memories, wherein at least two rows of the flash memories are connected to the flash memory controller in parallel,   wherein a plurality of independent parallel transmission channels are established between the SSD controller and the flash memory controllers, and data transmission between the host and the flash memory array is performed through the transmission channels under control of the DMA engine.   
   
   
       13 . The SSD storage system as claimed in  claim 12 , wherein the host writes data into the plurality of flash memories of the flash memory row in an interleaving manner. 
   
   
       14 . The SSD storage system as claimed in  claim 12 , wherein the host accesses the flash memory rows in parallel simultaneously. 
   
   
       15 . The SSD storage system as claimed in  claim 12 , wherein the high-speed serial connection interface is one of a SATA connection interface, a PCI Express connection interface, or a serial attached SCSI (SAS) connection interface. 
   
   
       16 . The SSD storage system as claimed in  claim 12 , wherein the host transmission interface is a MMC 4.0 or higher interface, the transmission interface host controller is a MMC host controller, and the flash memory controller is a MMC-flash memory controller. 
   
   
       17 . The SSD storage system as claimed in  claim 12 , wherein data transmission buses between the transmission interface host controllers and the flash memory controllers comprise 8-bit data buses, and 8-bit data buses are also arranged between the flash memory controllers and the flash memory rows connected in parallel. 
   
   
       18 . The SSD storage system as claimed in  claim 12 , wherein when the SSD controller receives an accessing request signal from the host, the microprocessor starts and sets the DMA engine, such that the DMA engine controls the data transmission between the host and the flash memory rows through the transmission channels. 
   
   
       19 . The SSD storage system as claimed in  claim 12 , wherein the high-speed serial connection interface is a SATA connection interface, and the SSD controller further comprises a SATA physical layer connection interface and a SATA controller, such that the SSD controller is connected to a SATA bus connection interface, so as to connect to a SATA host interface of the host. 
   
   
       20 . The SSD storage system as claimed in  claim 12 , wherein the flash memory controller further comprises a wear-leveling function, an error correction code (ECC) function, a garbage collection function, a bad block management (BBM) function or a combination thereof. 
   
   
       21 . A solid state disk (SSD) controller, connected to an external host via a high-speed serial bus connection interface, and connected to a plurality of flash memories via a plurality of flash memory controllers, the SSD controller comprising:
 a microprocessor;   a DMA engine, connected to the microprocessor for being controlled to be started, set and shut down by the microprocessor;   a buffer, coupled to the microprocessor and the DMA engine, for registering data;   a high-speed serial connection interface, connected to a host connection port of the host via the connected high-speed serial bus connection interface; and   a host transmission interface, having a plurality of transmission interface host controllers, wherein each of the transmission interface host controllers is connected to one of the flash memory controllers in parallel, and the flash memory controller is connected to at least two flash memories in parallel, and a plurality of independent parallel transmission channels are established between the SSD controller and the flash memory controllers, and data transmission between the host and the flash memories is performed through the transmission channels under control of the DMA engine.   
   
   
       22 . The SSD controller as claimed in  claim 21 , wherein the high-speed serial connection interface is one of a SATA connection interface, a PCI Express connection interface, or a SAS connection interface. 
   
   
       23 . The SSD controller as claimed in  claim 21 , further comprising a memory arbitrator connected to the high-speed serial connection interface, the microprocessor, and the host transmission interface, for arbitrating a priority sequence that the buffer to be accessed by the high-speed serial connection interface, the microprocessor, or the host transmission interface. 
   
   
       24 . The SSD controller as claimed in  claim 21 , wherein the host transmission interface is a MMC interface, the transmission interface host controller is a MMC host controller, and the flash memory controller is a MMC-flash memory controller. 
   
   
       25 . The SSD controller as claimed in  claim 21 , wherein data transmission buses between the transmission interface host controllers and the flash memory controllers comprise 8-bit data buses, and 8-bit data buses are also arranged between the flash memory controller and the flash memories connected in parallel.