Method of forming metal wiring layer of semiconductor device

Abstract

A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

1 . A method of forming a metal wiring layer of a semiconductor device, the method comprising:
 forming an insulating layer pattern defining a recess on a substrate;   forming a first barrier metal layer which extends over an upper surface of the insulating layer pattern, over a side wall of the insulating layer pattern that defines the sides of the recess, and along the bottom of the recess;   forming a second barrier metal layer on the first barrier metal layer including over that portion of the first barrier metal layer that overlies the upper surface of the insulating layer pattern and over a portion of the first barrier metal layer that extends within the recess, and wherein the forming of the second metal barrier layer is terminated when the second barrier metal layer extends over only a portion of the first barrier metal layer disposed within the recess such that part of the first barrier metal layer is left exposed after the second barrier metal layer has been formed;   filling a portion of the recess with conductive material while said part of the first barrier metal layer is exposed to thereby form damascene wiring; and forming an etch stop layer pattern in an upper portion of the recess which is not occupied by the damascene wiring.   
   
   
       2 . The method of  claim 1 , wherein said forming of the second barrier metal layer comprises forming a second barrier metal layer having a section within the recess that becomes thinner in a direction from the upper surface of the insulating layer towards the bottom of the recess. 
   
   
       3 . The method of  claim 1 , wherein the forming of the second barrier metal layer comprises forming a second barrier metal layer that has a first section extending over a sidewall of the insulating layer pattern that defines the sides of the recess and a second section that extends across the bottom of the recess, and wherein the second barrier metal layer has a discontinuity between the first and second sections thereof. 
   
   
       4 . The method of  claim 1 , wherein the first barrier metal layer and the second barrier metal layer are formed of TiN, respectively. 
   
   
       5 . The method of  claim 4 , wherein the ratio of N to Ti of the second barrier metal layer is smaller than that of the first barrier metal layer. 
   
   
       6 . The method of  claim 1 , wherein the first barrier metal layer is formed by a CVD process or an ALD process. 
   
   
       7 . The method of  claim 1 , wherein the second barrier metal layer is formed by a PVD process. 
   
   
       8 . The method of  claim 6 , wherein the second barrier metal layer is formed by a PVD process. 
   
   
       9 . The method of  claim 1 , wherein the forming of the damascene wiring comprises growing A1 from said part of the first barrier metal layer left exposed after the second barrier metal layer has been formed. 
   
   
       10 . The method of  claim 1 , wherein the forming of the etch stop layer pattern comprises forming a first etch stop film and subsequently forming a second etch stop film on the first etch stop film. 
   
   
       11 . The method of  claim 10 , wherein the forming of the etch stop layer pattern comprises:
 forming the first etch stop film and the second etch stop film to each extend over the upper surface of the insulating layer pattern as well as in the portion of the recess which is not occupied with the damascene wiring, and   subsequently selectively removing respective portions of the second etch stop film, the first etch stop film, the second barrier metal layer, and the first barrier metal layer to expose the upper surface of the insulating layer pattern.   
   
   
       12 . The method of  claim 1 , further comprising forming a contact hole aligned with the recess, after the etch stop layer pattern has been formed. 
   
   
       13 . A method of forming a metal wiring layer of a semiconductor device, the method comprising:
 forming an insulating layer pattern defining a recess on a substrate;   forming a first barrier metal layer which extends over an upper surface of the insulating layer pattern, over a side wall of the insulating layer pattern that defines the sides of the recess, and along the bottom of the recess;   forming a second barrier metal layer on the first barrier metal layer including over that portion of the first barrier metal layer that overlies the upper surface of the insulating layer pattern and over the first barrier metal within the recess, and wherein the forming of the second metal barrier layer comprises a PVD process that is terminated at a point in time at which the thickness of the second barrier metal layer varies in the depth-wise direction of the recess;   filling a portion of the recess with conductive material while said part of the first barrier metal layer is exposed to thereby form damascene wiring; and   forming an etch stop layer pattern in an upper portion of the recess which is not occupied by the damascene wiring.   
   
   
       14 . The method of  claim 13 , wherein the PVD process is a high density magnetron sputtering process.