US2009081566A1PendingUtilityA1
Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same
Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Sep 13, 2005Filed: Sep 23, 2008Published: Mar 26, 2009
Est. expirySep 13, 2025(expired)· nominal 20-yr term from priority
Inventors:Hung-Mo Yang
H10P 54/00H10W 46/501H10W 42/121H10W 20/493H10W 46/00G03F 1/44
53
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Claims
Abstract
A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scribe lanes and has a plurality of perforations, e.g. slit patterns engraved on each scribe lane. A photolithography reticle and method of manufacturing the wafer are also provided.
Claims
exact text as granted — not AI-modified1 . A reticle comprising:
a substrate including a plurality of chip areas and scribe lane areas, the substrate being transparent against exposure light; and a light-shielding pattern formed on the substrate and having a plurality of transparent portions in the scribe lane areas, the transparent portions corresponding to a plurality of slit patterns to be engraved on a passivation film formed on a wafer.
2 . The reticle of claim 1 , wherein the ends of the plurality of transparent portions corresponding to the plurality of slit patterns are not aligned with one another.
3 . The reticle of claim 1 , wherein the plurality of transparent portions corresponding to the plurality of slit patterns are alternately arranged so that end portions thereof are staggered along the length of the scribe lane.
4 . The reticle of claim 1 , wherein the scribe lane areas include areas not having monitoring patterns formed thereon and areas having monitoring patterns formed thereon, and
the light-shielding pattern shields light in the areas having monitoring patterns formed thereon.
5 . The reticle of claim 1 , wherein the light-shielding pattern in the chip areas includes transparent portions corresponding to fuse openings.
6 . The reticle of claim 5 , wherein the light-shielding pattern in the chip areas further includes transparent portions corresponding to pad openings.
7 . The reticle of claim 1 , wherein the width of an opening corresponding to a slit pattern at the central portion of each scribe lane area is larger than that at other portions of each scribe lane area.
8 . The reticle of claim 1 , wherein the width of openings corresponding to slit patterns near a central area of each scribe lane are gradually larger than the width of an opening corresponding to a slit pattern at an edge area of each scribe lane.
9 . A method of manufacturing a wafer, the method comprising:
forming a passivation film on a wafer, which includes scribe lanes formed between a plurality of chips; and engraving a plurality of slit patterns on the passivation film, the slit patterns being formed on the scribe lanes.
10 . The method of claim 9 , wherein the passivation film on the scribe lanes includes an enclosure pattern provided with bridges that connect together a plurality of passivation line patterns.
11 . The method of claim 9 , wherein the ends of the plurality of slit patterns are not aligned with one another.
12 . The method of claim 9 , wherein the plurality of slit patterns are alternately arranged.
13 . The method of claim 9 , wherein each of the scribe lanes includes first areas not having monitoring patterns formed thereon and second areas having monitoring patterns formed thereon, and
the first areas having monitoring patterns formed thereon do not include the engraved slit patterns and are covered with the passivation film.
14 . The method of claim 9 , wherein engraving the plurality of slit patterns includes simultaneously forming fuse openings on the passivation film.
15 . The method of claim 14 , wherein engraving the plurality of slit patterns includes simultaneously forming pad openings on the passivation film.
16 . The method of claim 9 , wherein engraving the plurality of slit patterns includes engraving the slit patterns such that the width of a slit pattern at the central portion of each scribe lane is larger than the width of a slit pattern at other portions of each scribe lane.
17 . A method of manufacturing a wafer comprising:
forming a passivation film on the wafer, the wafer including a scribe lane formed between adjacent chips thereon; selectively perforating the passivation film in a region overlying the scribe lane.
18 . The method of claim 17 , wherein the perforating of the passivation film forms a perforation that extends substantially entirely over the scribe lane.
19 . The method of claim 17 wherein the perforating is performed by engraving a plurality of slit patterns on the passivation film, the slit patterns extending lengthwise over the scribe lane.
20 . The method of claim 19 , wherein the slit patterns are substantially coextensive in two dimensions with the scribe lanes.Join the waitlist — get patent alerts
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