Semiconductor memory device

Abstract

A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

1 - 21 . (canceled) 
   
   
       22 . A semiconductor memory device comprising:
 a plurality of memory cells being divided into a plurality of blocks;   a memory cell selection circuit for selecting a memory cell in the memory cells;   a plurality of sense amplifier circuits arranged corresponding to the blocks, respectively, for sensing data of the memory cell selected by said memory cell selection circuit;   a first latch circuit arranged corresponding to a first group of data terminals for latching data sensed by said plurality of sense amplifier circuits in accordance with a first operation timing signal;   a second latch circuit arranged correspond to a second group of data terminals different from said first group, for latching and storing data sensed by said plurality of sense amplifier circuits in accordance with a second operation timing signal; and   a sense control circuit for activating the sense amplifier circuits according to said first operation timing and said second operation timing for a same address.   
   
   
       23 . The semiconductor memory device according to  claim 22 , wherein
 said memory cell selection circuit simultaneously selects memory cells storing data of a plurality of addresses in a selected block in said plurality of blocks and couples selected memory cells to the sense amplifier circuits in parallel, and   said semiconductor memory device further comprises:   a data selection circuit for selecting data of a predetermined number of bits, which forms data of external one address, in accordance with predetermined address bits from the first and second latch circuits and outputting selected data bits in parallel.   
   
   
       24 . The semiconductor memory device according to  claim 22 , wherein
 each of the memory cells stores multi-level data of more than three values;   data of a plurality of external addresses are stored in an internal one address in each block; and   either one of the upper data and lower data of said external one address is transferred from the sense amplifier circuits at the first timing and the other one of the upper data and lower data of said external one address is transferred from the sense amplifier circuits at the second timing.   
   
   
       25 . A semiconductor memory device comprising:
 a sense amplifier circuit for comparing a cell current driven by a selected memory cell with a reference current to sense data of the selected memory cell;   a sense amplifier control circuit for activating said sense amplifier circuit a plurality of times for a same address; and   a reference current setting circuit for setting a next reference current amount for a next sensing in accordance with a first data sensed first time by said sense amplifier.