Constant phase digital attenuator with on-chip matching circuitry

Abstract

Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit comprises an input node to receive an input signal to be attenuated, an output node to output an attenuated signal, a reference loss path between the input node and the output node, and an attenuation path between the input node and the output node. The reference loss path comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path and an effective phase length of the attenuation path may be equalized to provide a constant phase when the digital attenuator circuit is switched between states. Other embodiments are described and claimed.

1 . A digital attenuator circuit comprising:
 an input node to receive an input signal to be attenuated;   an output node to output an attenuated signal;   a reference loss path between the input node and the output node comprising switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR); and   an attenuation path between the input node and the output node comprising switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state,   wherein an effective phase length of the reference loss path and an effective phase length of the attenuation path are equalized to provide a constant phase when the digital attenuator circuit is switched between states.   
     
     
         2 . The digital attenuator circuit of  claim 1 , further comprising an interstage inductance element connected to at least one of the input node and the output node to match out parasitic reactance of the digital attenuator circuit. 
     
     
         3 . The digital attenuator circuit of  claim 2 , the interstage inductance element comprising a high impedance transmission line. 
     
     
         4 . The digital attenuator circuit of  claim 1 , the switching elements of the reference loss path comprising a plurality of series transistors; and the matching circuitry of the reference loss path comprising a shunt resistor connected to each of the plurality of series transistors. 
     
     
         5 . The digital attenuator circuit of  claim 4 , the switching elements of the reference loss path further comprising cascaded shunt transistors connected to each of the plurality of series transistors. 
     
     
         6 . The digital attenuator circuit of  claim 4 , the switching elements of the reference loss path further comprising a dual gate shunt transistor connected to each of the plurality of series transistors. 
     
     
         7 . The digital attenuator circuit of  claim 1 , the switching elements of the attenuation path comprising a plurality of series transistors; and the attenuating circuitry of the attenuation path comprising a PI network connected to each of the plurality of series transistors. 
     
     
         8 . The digital attenuator circuit of  claim 7 , the switching elements of the attenuation path further comprising cascaded shunt transistors connected to each of the plurality of series transistors. 
     
     
         9 . The digital attenuator circuit of  claim 7 , the switching elements of the attenuation path further comprising a dual gate shunt transistor connected to each of the plurality of series transistors. 
     
     
         10 . The digital attenuator circuit of  claim 7 , the PI network configured in accordance with an amount of attenuation to be provided by the digital attenuator circuit. 
     
     
         11 . A multi-stage digital attenuator comprising:
 a plurality of digital attenuator circuits, each digital attenuator circuit comprising a stage of the multi-stage digital attenuator circuit; and   a plurality of interstage inductance elements comprising high impedance transmission lines to match output of a previous stage and input of a next stage.   
     
     
         12 . The digital attenuator of  claim 11 , the plurality of digital attenuator circuits on a single chip. 
     
     
         13 . The digital attenuator of  claim 11 , each digital attenuator circuit comprising:
 a reference loss path comprising switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR); and   an attenuation path comprising switching elements and attenuating circuitry to attenuate an input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state,   wherein an effective phase length of the reference loss path and an effective phase length of the attenuation path are equalized to provide a constant phase when the digital attenuator circuit is switched between states.   
     
     
         14 . The digital attenuator of  claim 13 , the switching elements of the reference loss path comprising a plurality of series transistors; and the matching circuitry of the reference loss path comprising a shunt resistor connected to each of the plurality of series transistors. 
     
     
         15 . The digital attenuator of  claim 14 , the switching elements of the reference loss path further comprising cascaded shunt transistors connected to each of the plurality of series transistors. 
     
     
         16 . The digital attenuator of  claim 14 , the switching elements of the reference loss path further comprising a dual gate shunt transistor connected to each of the plurality of series transistors. 
     
     
         17 . The digital attenuator of  claim 13 , the switching elements of the attenuation path comprising a plurality of series transistors; and the attenuating circuitry of the attenuation path comprising a PI network connected to each of the plurality of series transistors. 
     
     
         18 . The digital attenuator of  claim 17 , the switching elements of the attenuation path further comprising cascaded shunt transistors connected to each of the plurality of series transistors. 
     
     
         19 . The digital attenuator of  claim 17 , the switching elements of the attenuation path further comprising a dual gate shunt transistor connected to each of the plurality of series transistors. 
     
     
         20 . The digital attenuator of  claim 17 , the PI network configured in accordance with an amount of attenuation to be provided by the digital attenuator circuit. 
     
     
         21 . A method comprising:
 providing a digital attenuator circuit on a chip, the digital attenuator circuit comprising:   a reference loss path comprising switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR); and   an attenuation path comprising switching elements and attenuating circuitry to attenuate an input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state,   wherein an effective phase length of the reference loss path and an effective phase length of the attenuation path are equalized to provide a constant phase when the digital attenuator circuit is switched between states.   
     
     
         22 . The method of  claim 21 , further comprising:
 providing a plurality of the digital attenuator circuits on the chip to implement a multi-stage digital attenuator.   
     
     
         23 . The method of  claim 22 , further comprising:
 providing interstage inductance elements for coupling digital attenuator circuits.   
     
     
         24 . The method of  claim 23 , the interstage inductance elements comprising high impedance transmission lines.