Integrated Half-Bridge Power Circuit

Abstract

A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

1 - 12 . (canceled) 
     
     
         13 . A method of switching an electrical load, the method comprising:
 providing a power-converter that includes an integrated circuit having a high-side switch, a low-side switch and a substrate, wherein the high-side switch is a Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS FET), and the conductivity-type of the LDMOS FET and the conductivity of the substrate are of the same type.   
     
     
         14 . A method as recited in  claim 13 , wherein the low-side switch is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) FET. 
     
     
         15 . A method as recited in  claim 13 , wherein the low-side switch is a vertical trench Double Diffused Metal Oxide Semiconductor (DMOS) FET. 
     
     
         16 . A method as recited in  claim 13 , wherein low-side switch is another Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) FET. 
     
     
         17 . A method as recited in  claim 14 , wherein the power converter further comprises a plurality of conductive plugs, which provide an ohmic connection of a few milli-Ohms to an output on a surface of a substrate. 
     
     
         18 . A method as recited in  claim 15 , wherein the power converter further comprises a plurality of conductive plugs, which provide an, ohmic connection of a few milli-Ohms to an output on a surface of a substrate. 
     
     
         19 . A method as recited in  claim 16 , wherein the power converter further comprises a plurality of conductive plugs, which provide an ohmic connection of a few milli-Ohms to an output on a surface of a substrate. 
     
     
         20 . A method as recited in  claim 13 , wherein the high side switch is a Control FET (CF), and the lowside switch is a Synchronous Rectifier FET (SF). 
     
     
         21 . An integrated circuit comprising:
 a substrate having a first conductivity type;   a first transistor including a source region that is disposed in a first well in the substrate, the first well having a second conductivity type   a second transistor including a source region that is disposed in a second well in the substrate, a drain region, and a body region that is disposed in the second well, the second well having the first conductivity type, wherein the source region of the first transistor is connected to the drain region of the second transistor.   
     
     
         22 . The integrated circuit of  claim 21 , further comprising a source contact that connects the source region of the first transistor to the drain region of the second transistor, and a conductive plug of the first conductivity type in the substrate, wherein the conductive plug is connected to the source contact and the conductive plug separates the first well from the second well. 
     
     
         23 . The integrated circuit of  claim 22 , wherein the first and second transistors are both lateral double-diffused metal oxide semiconductor type transistors. 
     
     
         24 . The integrated circuit of  claim 21 , further comprising a source contact and a conductive plug of the first conductivity type in the substrate, wherein the drain region of the second transistor is formed by a portion of the substrate, the source contact is connected to the source region of the first transistor and to the conductive plug, and the conductive plug is connected to the drain region of the second transistor. 
     
     
         25 . The integrated circuit of  claim 24 , wherein the conductive plug separates the first well from the second well. 
     
     
         26 . The integrated circuit of  claim 21 , wherein the second transistor further includes a trench gate that is disposed in the second well. 
     
     
         27 . The integrated circuit of  claim 21 , wherein the first transistor is a lateral double-diffused metal oxide semiconductor type transistor. 
     
     
         28 . The integrated circuit of  claim 24 , wherein the second transistor is a vertical double-diffused metal oxide semiconductor type transistor. 
     
     
         29 . The integrated circuit of  claim 21 , further comprising one or more field effect transistors that are configured to control gate switching of the first and second transistors. 
     
     
         30 . The integrated circuit of  claim 21 , wherein the first transistor is a control transistor of a down convertor and the second transistor is a synchronous rectifier of the down convertor. 
     
     
         31 . The integrated circuit of  claim 21 , further comprising an inductor and a capacitor, wherein a source contact of the first transistor and a drain contact of the second transistor are connected to a first side of the inductor, and the capacitor is connected to a second side of the transistor. 
     
     
         32 . The integrated circuit of  claim 21 , wherein the first transistor further includes a drain region and a body region that are each disposed in the first well.