Method for forming a dielectric stack

Abstract

The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.

1 . A dielectric stack in an integrated circuit comprising
 a high-k dielectric layer comprising a high-k material;   a dielectric layer comprising silicon and nitrogen; and   an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.   
     
     
         2 . The dielectric stack of  claim 1 , wherein a crystallization temperature of the dielectric stack is higher than a crystallization temperature of the high-k material. 
     
     
         3 . The dielectric stack of  claim 1 , wherein a crystallization temperature of the dielectric stack is from 800 degrees Celsius to 1200 degrees Celsius. 
     
     
         4 . The dielectric stack of  claim 1 , wherein the dielectric stack comprises a sequence of the high-k dielectric layer, the intermediate layer, and the dielectric layer repeated from 3 times to 60 times. 
     
     
         5 . The dielectric stack of  claim 4 , wherein an intermediate layer is disposed between one of the high-k dielectric layers and an adjacent dielectric layer. 
     
     
         6 . The dielectric stack of  claim 1 , wherein the dielectric layer further comprises oxygen. 
     
     
         7 . The dielectric stack of  claim 1 , wherein the dielectric layer comprises essentially no high-k material, 
     
     
         8 . The dielectric stack of  claim 1 , wherein the high-k dielectric layer comprises a compound selected from the group consisting of a transition metal oxide and transition metal oxynitride. 
     
     
         9 . The dielectric stack of  claim 1 , wherein the high-k dielectric layer comprises a compound selected from the group consisting of ZrO 2 , HfO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , HfO x N y , HfN, and mixtures thereof. 
     
     
         10 . The dielectric stack of  claim 1 , wherein the high-k dielectric layer has a thickness of from 0.5 nm to 20 nm. 
     
     
         11 . The dielectric stack of  claim 1 , wherein the dielectric layer has a thickness of from 0.5 nm to 20 nm. 
     
     
         12 . The dielectric stack of  claim 1 , wherein the intermediate layer comprises Hf, nitrogen, silicon, and oxygen. 
     
     
         13 . The dielectric stack of  claim 1 , wherein the dielectric layer comprises a material selected from the group consisting of SiN, SiON, and Si 3 N 4 . 
     
     
         14 . The dielectric stack of  claim 1 , wherein the high-k dielectric layer is formed by an atomic layer deposition process. 
     
     
         15 . A MOS transistor comprising:
 a gate electrode;   a channel region having an upper surface underlying the gate electrode; and   a dielectric stack interposed between the gate electrode and the upper surface of the channel region, the dielectric stack comprising:
 a high-k dielectric layer comprising a high-k material, 
 a dielectric layer comprising silicon and nitrogen, and 
 an intermediate layer between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.