Semiconductor Memory Device

Abstract

Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1 , an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

1 . A semiconductor memory device having an error correction function of correcting a defective bit, comprising:
 a counter that counts the number of error corrections;   an upper limit setting section that, when an upper limit setting signal is inputted externally, sets a count result of the number of error corrections in the counter as an upper limit of the number of error corrections; and   a comparator that compares the upper limit with the count result in the counter after the passing of a predetermined time.   
     
     
         2 . A semiconductor memory device having an error correction function of correcting a defective bit, comprising:
 a counter that counts the number of error corrections;   an upper limit setting section that stores an upper limit of the number of error corrections and that, when an upper limit setting signal is externally inputted after completion of the counting in the counter, increments or decrements the upper limit in synchronization with a clock signal; and   a comparator that compares the count result in the counter with the upper limit.   
     
     
         3 . A semiconductor memory device having an error correction function of correcting a defective bit, comprising:
 an error correction memory section that stores error correction information of whether or not the error correction is performed, at every combination of data bits and parity bits required to construct a code capable of 1-bit error correction.   
     
     
         4 . The semiconductor memory device according to  claim 3 , wherein the error correction memory section is a surplus section resulting from allocating a memory cell array configured by a 4-bit or 8-bit unit to data bits and parity bits required to construct the code capable of 1-bit error correction. 
     
     
         5 . The semiconductor memory device according to  claim 3 , further comprising:
 a counter that counts the number of error corrections based on the error correction information.