Polishing pad, method of producing the same and method of producing semiconductor device by using the same

Abstract

The present invention provides a polishing pad used for planarizing inter layer dielectrics and the like by CMP (chemical mechanical polishing) in the manufacturing process of a semiconductor device, a method of producing the polishing pad and a method of producing a semiconductor device by using the polishing pad. The present invention relates to a semiconductor wafer polishing pad having grooves in a polishing surface and formed from a foamed polyurethane, wherein a processed surface of the groove comprising a side surface and a bottom surface has a surface roughness Ra of not more than 10.

1 . A semiconductor wafer polishing pad having grooves in a polishing surface and formed from a foamed polyurethane, wherein a processed surface of a groove formed in a side surface and a bottom surface has a surface roughness Ra of not more than 10 μm. 
     
     
         2 . The polishing pad according to  claim 1 , wherein the processed surface of the groove has a surface roughness Ra of 1 to 9 μm. 
     
     
         3 . A semiconductor wafer polishing pad comprising a polishing layer formed from a porous material and having, a polishing surface of the polishing layer with grooves formed therein,
 wherein at least one portion of an inner surface of the groove has a non-porous surface having a surface roughness Ra of 1.0 to 5.0 μm.   
     
     
         4 . (canceled) 
     
     
         5 . The polishing pad according to  claim 3 , wherein the groove has a depth of 0.5 to 1.5 mm. 
     
     
         6 . The polishing pad according to  claim 3  or  5 , wherein the polishing layer is formed from a porous material having an average cell diameter of 20 to 70 μm. 
     
     
         7 . The polishing pad according to  claim 3  or  5 , wherein the polishing layer has a specific gravity of 0.5 to 1.0 g/cm 3 . 
     
     
         8 . The polishing pad according to  claim 3  or  5 , wherein the polishing layer has a compressibility of 0.5 to 5.0%. 
     
     
         9 . The polishing pad according to  claim 3  or  5 , wherein the polishing layer has a hardness of 45 to 65. 
     
     
         10 . The polishing pad according to  claim 3  or  5 , further comprising a cushion layer, wherein the cushion layer has lower hardness than the polishing layer. 
     
     
         11 . A method of producing a semiconductor wafer polishing pad comprising a step of mechanical cutting by stepwise varying a feed speed and feed amount of a groove processing tool to form concentric circular grooves having rectangle sectional shape on the polishing surface. 
     
     
         12 . The method according to  claim 11 , wherein the step of forming the grooves comprises stopping the feed of the groove processing tool for a certain time at the position that the groove processing tool reaches a desired depth. 
     
     
         13 . The method according to  claim 11 , wherein the feed speed and feed amount of a groove processing tool are stepwise varied and increased in order of precedence. 
     
     
         14 . The method according to  claim 11 , wherein the polishing pad is formed from a foamed polyurethane. 
     
     
         15 . A method of producing a semiconductor device comprising at least a step of polishing the surface of a semiconductor wafer by using the polishing pad according to anyone of  claims 1  to  3  and  5  to  10 . 
     
     
         16 . The polishing pad according to  claim 6 , wherein the polishing layer has a specific gravity of 0.5 to 1.0 g/cm 3 . 
     
     
         17 . The polishing pad according to  claim 16 , wherein the polishing layer has a compressibility of 0.5 to 5.0%. 
     
     
         18 . The polishing pad according to  claim 16 , wherein the polishing layer has a hardness of 45 to 65. 
     
     
         19 . The polishing pad according to  claim 16 , further comprising a cushion layer, wherein the cushion layer has lower hardness than the polishing layer.