US2009075471A1PendingUtilityA1

Method of manufacturing semiconductor memory device

Assignee: RENESAS TECH CORPPriority: Sep 22, 2005Filed: Nov 10, 2008Published: Mar 19, 2009
Est. expirySep 22, 2025(expired)· nominal 20-yr term from priority
H10W 10/021H10W 10/20H10D 64/035H10B 41/30H10B 69/00
50
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Claims

Abstract

A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.

Claims

exact text as granted — not AI-modified
1 - 9 . (canceled) 
     
     
         10 . A method of manufacturing a semiconductor device comprising:
 forming a first interconnect line on a main surface of a semiconductor substrate with a first electrically insulating film therebetween;   forming a second interconnect line on the main surface of said semiconductor substrate with a second electrically insulating film therebetween to extend along said first interconnect line;   forming a first electrically conductive film on a top surface of said first interconnect line such that the first electrically conductive film is larger than said first interconnect line in width in the direction parallel with the main surface of said semiconductor substrate;   forming a second electrically conductive film on a top surface of said second interconnect line such that the second electrically conductive film is larger than said second interconnect line in width in the direction parallel with the main surface of said semiconductor substrate;   forming a third electrically insulating film to cover said first electrically conductive film and said second electrically conductive film;   forming a first region where the distance between said first interconnect line and said second interconnect line is at most a predetermined value;   forming a second region where the distance between said first interconnect line and said second interconnect line is larger than said predetermined value; and   forming a gap that is in said first region where said first electrically conductive film and said second electrically conductive film are formed and that is formed in said third electrically insulating film between said first interconnect line and said second interconnect line located in said first region.   
     
     
         11 . The method according to  claim 10 , wherein
 said first interconnect line and said first electrically conductive film contact each other,   said second interconnect line and said second electrically conductive film contact each other,   said first electrically conductive film is weaker in ionization tendency than said first interconnect line, and   said second electrically conductive film is weaker in ionization tendency than said second interconnect line.

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