Solid-state image capturing apparatus and electronic information device

Abstract

A solid-state image capturing apparatus comprises a pixel array in which pixel sections for outputting a pixel signal in accordance with incident light are arranged in two dimensions, and a readout signal line arranged for each pixel section column on the pixel array, for reading out a pixel signal from each pixel section in each pixel section column, where each pixel section includes a light receiving section for performing photoelectric conversion on incident light; a signal charge storing section for storing a signal charge generated in the light receiving section and generating electric potential in accordance with the stored signal charge; and a reset transistor for resetting electric potential of the signal charge storing section to reset electric potential.

1 . A solid-state image capturing apparatus, comprising a pixel array in which pixel sections for outputting a pixel signal in accordance with incident light are arranged in two dimensions, and a readout signal line arranged for each pixel section column on the pixel array, for reading out a pixel signal from each pixel section in each pixel section column,
 wherein each pixel section includes:   a light receiving section for performing photoelectric conversion on the incident light;   a signal charge storing section for storing a signal charge generated in the light receiving section and generating electric potential in accordance with the stored signal charge; and   a reset transistor for resetting the electric potential of the signal charge storing section to reset electric potential,   wherein a reset drain wiring for supplying the reset electric potential to a drain of the reset transistor being positioned above a plurality of pixel sections in the pixel array in such a manner to cross the center of each pixel section.   
   
   
       2 . A solid-state image capturing apparatus according to  claim 1 , wherein a wiring layer, which constitutes the reset drain wiring, is formed by a second layer metal wiring of multiple layer wirings that are laminated with alternately interposed insulation films on the pixel array, and is connected to a drain region in the drain region of the reset transistor via a first layer metal wiring formed on the pixel array. 
   
   
       3 . A solid-state image capturing apparatus according to  claim 2 , wherein the first layer metal wiring, which connects the drain region and the reset drain wiring constituted of the second layer metal wiring, in the drain region of the reset transistor is positioned only in the drain region so as to be located at the center of the pixel section. 
   
   
       4 . A solid-state image capturing apparatus according to  claim 1 , wherein the light receiving section is constituted of two photodiodes positioned in an opposing manner on both sides of the signal charge storing section. 
   
   
       5 . A solid-state image capturing apparatus according to  claim 4 , wherein the pixel section includes two transfer transistors for transferring the signal charge from each photodiode to the signal charge storing section, the two transfer transistors corresponding to the two photodiodes. 
   
   
       6 . A solid-state image capturing apparatus according to  claim 5 , wherein the photodiode is an embedded photodiode. 
   
   
       7 . A solid-state image capturing apparatus according to  claim 5 ,
 wherein two diffusion regions, which constitute each of the photodiodes, are connected to a diffusion region, which is located in between the two diffusion regions and constitutes the signal charge storing section, and   wherein a gate electrode of each of the transfer transistors is positioned above a connecting portion between a diffusion region constituting the photodiode and a diffusion region constituting the signal charge storing section.   
   
   
       8 . A solid-state image capturing apparatus according to  claim 7 , wherein:
 the diffusion region constituting the photodiode is a rectangle;   the diffusion region constituting the signal charge storing section is a longitudinally elongated rectangle;   the gate electrode of each of the transfer transistors is positioned at a corner of the rectangular diffusion region that constitutes the photodiode, and is positioned diagonally to a side edge of the rectangle.   
   
   
       9 . A solid-state image capturing apparatus according to  claim 4 , wherein the reset drain wiring is positioned in between two opposing photodiodes that constitute the pixel section. 
   
   
       10 . A solid-state image capturing apparatus according to  claim 5 , wherein the pixel section includes one amplifying transistor for amplifying electric potential of the signal charge storing section to read out the electric potential to the readout signal line. 
   
   
       11 . A solid-state image capturing apparatus according to  claim 1 , wherein a first voltage is applied to the reset drain wiring when the pixel section connected to the reset drain wiring is selected, and a second voltage is applied to the reset drain wiring when the pixel section connected to the reset drain is not selected, the first voltage being higher than or equal to the second voltage. 
   
   
       12 . A solid-state image capturing apparatus according to  claim 11 , wherein the first voltage is higher than or equal to power source voltage, and the second voltage is higher than or equal to 0V. 
   
   
       13 . A solid-state image capturing apparatus according to  claim 1 , wherein the light receiving section, which constitutes the pixel section, is constituted of a plurality of photoelectric conversion elements. 
   
   
       14 . A solid-state image capturing apparatus according to  claim 13 , wherein the light receiving section, which constitutes the pixel section, is constituted of two or four photoelectric conversion elements. 
   
   
       15 . A solid-state image capturing apparatus according to  claim 1 , wherein the solid-state image capturing apparatus includes a buffer circuit for applying the first voltage or the second voltage to the reset drain wiring. 
   
   
       16 . A solid-state image capturing apparatus according to  claim 15 , wherein the buffer circuit is constituted of a CMOS inverter, which is constituted of a P-type MOS transistor and an N-type MOS transistor that are connected in series between a node, to which the first voltage is supplied, and a node, to which the second voltage is supplied. 
   
   
       17 . A solid-state image capturing apparatus according to  claim 15 , further including a boost circuit for boosting the first voltage supplied to the buffer circuit more than power source voltage. 
   
   
       18 . An electronic information device comprising an image capturing section, in which the solid-state image capturing apparatus according to  claim 1  is used for the image capturing section.