Three dimensional structure memory

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

1 - 87 . (canceled) 
   
   
       88 . A stacked integrated circuit memory comprising:
 at least one logic integrated circuit, wherein the at least one logic layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit;   at least one thinned substantially flexible memory integrated circuit positioned in a stacked relation to one another; and   interconnections electrically connecting the at least one logic integrated circuit and the at least one thinned substantially flexible memory integrated circuit.   
   
   
       89 . The device of  claim 88 , wherein the interconnections electrically connecting the at least one thinned substantially flexible memory controller integrated circuit and the at least one thinned substantially flexible memory integrated circuit are vertical interconnections internal to the stacked integrated circuit. 
   
   
       90 . The device of  claim 88 , wherein at least one of the thinned substantially flexible logic integrated circuit and the at least one thinned substantially flexible memory integrated circuit are one of a single crystal semiconductor material and polycrystalline semiconductor material. 
   
   
       91 . The device of  claim 88 , wherein at least one of the at least one thinned substantially flexible logic integrated circuit and the at least one thinned substantially flexible memory integrated circuit have a thickness of less than about 50 microns. 
   
   
       92 . The device of  claim 88 , wherein at least one of the at least one thinned substantially flexible logic integrated circuit and the at least one thinned substantially flexible memory integrated circuit have a thickness of less than about 10 microns. 
   
   
       93 . The device of  claim 88 , wherein the at least one thinned substantially flexible memory integrated circuit has a different process technology from the at least one thinned substantially flexible memory controller integrated circuit. 
   
   
       94 . The device of  claim 131 , wherein the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance. 
   
   
       95 . The device of  claim 88 , wherein at least one of the thinned substantially flexible logic integrated circuit and the at least one thinned substantially flexible memory integrated circuit comprise active circuit devices and passive circuit devices. 
   
   
       96 . The device of  claim 88 , further comprising at least two logic integrated circuits, wherein a plurality of data bytes are transferred between the logic integrated circuits. 
   
   
       97 . The device of  claim 88 , further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry. 
   
   
       98 . The device of  claim 88 , further comprising at least one data function, wherein the data function is one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing. 
   
   
       99 . The device of  claim 88 , further comprising:
 a plurality of data lines;   a plurality of gate lines;   an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;   a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and   a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.   
   
   
       100 . The device of  claim 99 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 
   
   
       101 . The device of  claim 99 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines. 
   
   
       102 . The device of  claim 99 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell. 
   
   
       103 . The device of  claim 99 , wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells. 
   
   
       104 . The device of  claim 99 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory. 
   
   
       105 . The device of  claim 99 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line. 
   
   
       106 . The device of  claim 99 , wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory. 
   
   
       107 . A stacked integrated circuit memory comprising:
 a logic layer, wherein the logic layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit;   at least one thin substantially flexible memory layer formed overlying the logic layer; and   a plurality of connections internal to the stacked integrated circuit for transferring a plurality of data bytes between the logic layer and the at least one thin substantially flexible memory layer.   
   
   
       108 . The device of  claim 107 , wherein the interconnections electrically connecting the logic layer and the at least one memory layer are vertical interconnections internal to the stacked integrated circuit. 
   
   
       109 . The device of  claim 107 , wherein the logic layer and the at least one memory layer are one of a single crystal semiconductor material and polycrystalline semiconductor material. 
   
   
       110 . The device of  claim 107 , wherein at least one of the logic layer and the at least one memory layer have a thickness of less than about 50 microns. 
   
   
       111 . The device of  claim 107 , wherein at least one of logic layer and the at least one memory layer have a thickness of less than about 10 microns. 
   
   
       112 . The device of  claim 107 , wherein the at least one memory layer has a different process technology from one of the logic layer. 
   
   
       113 . The device of  claim 112 , wherein the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance. 
   
   
       114 . The device of  claim 107 , wherein the logic layer and the at least one memory layer comprise at least one of active circuit devices and passive circuit devices. 
   
   
       115 . The device of  claim 107 , further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry. 
   
   
       116 . The device of  claim 107 , further comprising at least one data function, wherein the data function is one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing. 
   
   
       117 . The device of  claim 107 , further comprising:
 a plurality of data lines;   a plurality of gate lines;   an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;   a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and   a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.   
   
   
       118 . The device of  claim 117 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 
   
   
       119 . The device of  claim 117 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines. 
   
   
       120 . The device of  claim 117 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell. 
   
   
       121 . The device of  claim 117 , wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells. 
   
   
       122 . The device of  claim 117 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory. 
   
   
       123 . The device of  claim 117 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line. 
   
   
       124 . The device of  claim 117 , wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory. 
   
   
       125 . An integrated circuit comprising:
 a data source in one integrated circuit layer formed with a low stress dielectric, wherein the integrated circuit layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit;   a data sink in a circuit layer formed overlying the data source integrated circuit layer, there being a volume within which the integrated circuit and circuit layer overlie one another; and   interconnect circuitry within said volume for transferring control signals and a plurality of data bytes between the data source and data sink.   
   
   
       126 . The device of  claim 125 , wherein the interconnections electrically connecting the data source and the data sink are vertical interconnections internal to the stacked integrated circuit. 
   
   
       127 . The device of  claim 125 , wherein the data source and the data sink are one of a single crystal semiconductor material and polycrystalline semiconductor material. 
   
   
       128 . The device of  claim 125 , wherein at least one of the data source and the data sink have a thickness of less than about 50 microns. 
   
   
       129 . The device of  claim 125 , wherein at least one of the data source and the data sink have a thickness of less than about 10 microns. 
   
   
       130 . The device of  claim 125 , wherein the data source has a different process technology from the data sink. 
   
   
       131 . The device of  claim 130 , wherein the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance. 
   
   
       132 . The device of  claim 125 , wherein the data source and the data sink comprise at least one of active circuit devices and passive circuit devices. 
   
   
       133 . The device of  claim 125 , wherein the data source and the data sink are logic integrated circuits, wherein a plurality of data bytes are transferred between the logic integrated circuits. 
   
   
       134 . The device of  claim 125 , further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry. 
   
   
       135 . The device of  claim 125 , further comprising at least one data function, wherein the data function is one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing. 
   
   
       136 . The device of  claim 125 , further comprising:
 a plurality of data lines;   a plurality of gate lines;   an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;   a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and   a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.   
   
   
       137 . The device of  claim 136 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 
   
   
       138 . The device of  claim 136 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines. 
   
   
       139 . The device of  claim 136 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell. 
   
   
       140 . The device of  claim 136 , wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells. 
   
   
       141 . The device of  claim 136 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory. 
   
   
       142 . The device of  claim 136 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line. 
   
   
       143 . The device of  claim 136 , wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory. 
   
   
       144 . An integrated circuit comprising:
 a data source in one integrated circuit layer formed with a low stress dielectric, wherein the integrated circuit layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit;   a data sink in a circuit layer overlying the data source integrated circuit layer, there being a volume within which the integrated circuit and circuit layer overlie one another; and   interconnect circuitry within said volume for transferring control signals and a plurality of data bytes between the data source and data sink.   
   
   
       145 . The device of  claim 144 , wherein the interconnections electrically connecting the data source and the data sink are vertical interconnections internal to the stacked integrated circuit. 
   
   
       146 . The device of  claim 144 , wherein the data source and the data sink are one of a single crystal semiconductor material and polycrystalline semiconductor material. 
   
   
       147 . The device of  claim 144 , wherein at least one of the data source and the data sink have a thickness of less than about 50 microns. 
   
   
       148 . The device of  claim 144 , wherein at least one of the data source and the data sink have a thickness of less than about 10 microns. 
   
   
       149 . The device of  claim 144 , wherein the data source has a different process technology from the data sink. 
   
   
       150 . The device of claim  187 , wherein the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance. 
   
   
       151 . The device of  claim 144 , wherein the data source and the data sink comprise at least one of active circuit devices and passive circuit devices. 
   
   
       152 . The device of  claim 144 , wherein the data source and the data sink are logic integrated circuits, wherein a plurality of data bytes are transferred between the logic integrated circuits. 
   
   
       153 . The device of  claim 144 , further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry. 
   
   
       154 . The device of  claim 144 , further comprising at least one data function, wherein the data function is one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing. 
   
   
       155 . The device of  claim 144 , further comprising:
 a plurality of data lines;   a plurality of gate lines;   an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;   a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and   a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.   
   
   
       156 . The device of  claim 155 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 
   
   
       157 . The device of  claim 155 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines. 
   
   
       158 . The device of  claim 155 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell. 
   
   
       159 . The device of  claim 155 , wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells. 
   
   
       160 . The device of  claim 155 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory. 
   
   
       161 . The device of  claim 155 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line. 
   
   
       162 . The device of  claim 155 , wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory. 
   
   
       163 . An integrated circuit comprising:
 a data source in a first circuit layer formed with a low stress dielectric, wherein the first circuit layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit;   a data sink in a second circuit layer;   the first and second circuit layers substantially overlie each other; and   interconnect circuitry between the data source and data sink interconnecting the data source and data sink for transferring control signals between the data source and the data sink and for transferring a plurality of data bytes between the data source and data sink.   
   
   
       164 . The device of  claim 163 , wherein the interconnections electrically connecting the data source and the data sink are vertical interconnections internal to the stacked integrated circuit. 
   
   
       165 . The device of  claim 163 , wherein the data source and the data sink are one of a single crystal semiconductor material and polycrystalline semiconductor material. 
   
   
       166 . The device of  claim 163 , wherein at least one of the data source and the data sink have a thickness of less than about 50 microns. 
   
   
       167 . The device of  claim 163 , wherein at least one of the data source and the data sink have a thickness of less than about 10 microns. 
   
   
       168 . The device of  claim 163 , wherein the data source has a different process technology from the data sink. 
   
   
       169 . The device of  claim 168 , wherein the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance. 
   
   
       170 . The device of  claim 163 , wherein the data source and the data sink comprise at least one of active circuit devices and passive circuit devices. 
   
   
       171 . The device of  claim 163 , wherein the data source and the data sink are logic integrated circuits, wherein a plurality of data bytes are transferred between the logic integrated circuits. 
   
   
       172 . The device of  claim 163 , further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry. 
   
   
       173 . The device of  claim 163 , further comprising at least one data function, wherein the data function is one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing. 
   
   
       174 . The device of  claim 163 , further comprising:
 a plurality of data lines;   a plurality of gate lines;   an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;   a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and   a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.   
   
   
       175 . The device of  claim 174 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 
   
   
       176 . The device of  claim 174 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines. 
   
   
       177 . The device of  claim 174 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell. 
   
   
       178 . The device of  claim 174 , wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells. 
   
   
       179 . The device of  claim 174 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory. 
   
   
       180 . The device of  claim 174 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line. 
   
   
       181 . The device of  claim 174 , wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory.