Non-volatile memory devices

Abstract

According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

1 . A semiconductor fin on a semiconductor substrate, the semiconductor fin comprising:
 a plurality of semiconductor patterns vertically stacked; and   at least one of the plurality of semiconductor patterns including two portions horizontally spaced apart.   
     
     
         2 . The semiconductor fin of  claim 1 , wherein every other semiconductor pattern of the plurality of semiconductor patterns vertically stacked includes two portions horizontally spaced apart. 
     
     
         3 . The semiconductor fin of  claim 2 , wherein the semiconductor pattern including two portions horizontally spaced apart comprises a material having etching selectivity with respect to the semiconductor pattern vertically adjacent the semiconductor pattern including two portions horizontally spaced apart. 
     
     
         4 . The semiconductor fin of  claim 3 , wherein the semiconductor pattern including two portions horizontally spaced apart comprises silicon-germanium and the semiconductor pattern vertically adjacent the semiconductor pattern including two portions horizontally spaced apart comprises silicon. 
     
     
         5 . The semiconductor fin of  claim 2 , wherein at least one of the plurality of semiconductor patterns vertically stacked has a rounded periphery. 
     
     
         6 . The semiconductor fin of  claim 2 , wherein the two portions horizontally spaced apart, and upper and lower semiconductor patterns vertically adjacent the two portions horizontally spaced apart define a hole. 
     
     
         7 . The semiconductor fin of  claim 6 , wherein a vertical width of the hole is defined by a distance between the upper and lower semiconductor patterns vertically adjacent the two portions horizontally spaced apart and a horizontal width of the hole is defined by a distance between the two portions horizontally spaced apart. 
     
     
         8 . The semiconductor fin of  claim 1 , wherein the semiconductor substrate has a semiconductor pattern, and the plurality of semiconductor patterns vertically stacked are disposed on the semiconductor pattern of the semiconductor substrate. 
     
     
         9 . The semiconductor fin of  claim 8 , wherein the two portions horizontally spaced apart comprise a material having etching selectivity with respect to the semiconductor pattern of the semiconductor substrate and the semiconductor pattern vertically adjacent the two portions horizontally spaced apart. 
     
     
         10 . The semiconductor fin of  claim 9 , wherein the semiconductor pattern of the semiconductor substrate comprises silicon, the two portions horizontally spaced apart comprise silicon-germanium, and the semiconductor pattern vertically adjacent the two portions horizontally spaced apart comprises silicon. 
     
     
         11 . The semiconductor fin of  claim 8 , wherein at least one of the plurality of semiconductor patterns vertically stacked has a rounded periphery. 
     
     
         12 . The semiconductor fin of  claim 8 , every other semiconductor pattern of the plurality of semiconductor patterns vertically stacked includes two portions horizontally spaced apart, and the semiconductor pattern of the semiconductor substrate contacts the semiconductor pattern including the two portions horizontally spaced apart. 
     
     
         13 . The semiconductor fin of  claim 1 , further comprising an insulating pattern between the semiconductor substrate and the plurality of semiconductor patterns vertically stacked. 
     
     
         14 . A semiconductor device comprising a semiconductor fin on a semiconductor substrate, the semiconductor fin comprising:
 a plurality of semiconductor patterns vertically stacked on the semiconductor substrate, the semiconductor fin having a hole penetrating every other semiconductor pattern of the plurality of semiconductor patterns vertically stacked such that every other semiconductor pattern is divided into two portions horizontally spaced apart.   
     
     
         15 . The semiconductor device of  claim 14  further comprising a gate filling the hole and wrapping around the semiconductor pattern vertically adjacent the hole. 
     
     
         16 . The semiconductor device of  claim 15  further comprising a tunnel insulating layer and a blocking insulating layer sandwiching a charge storage layer, and further comprising the charge storage layer and the gate sandwiching the blocking insulating layer. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the semiconductor pattern being divided into two portions horizontally spaced apart comprises a material having etching selectivity with respect to semiconductor pattern vertically adjacent the two portions horizontally spaced apart. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the semiconductor pattern being divided into two portions horizontally spaced apart comprises silicon-germanium, and the semiconductor pattern vertically adjacent the two portions horizontally spaced apart comprises silicon. 
     
     
         19 . The semiconductor device of  claim 16 , each of the plurality of semiconductor patterns vertically stacked has a rounded periphery. 
     
     
         20 . The semiconductor device of  claim 15  further comprising a gate insulating layer between the gate and the semiconductor fin. 
     
     
         21 . The semiconductor device of  claim 20 , wherein each of the plurality of semiconductor patterns vertically stacked has a rounded periphery. 
     
     
         22 . A semiconductor fin for use in an active channel, the semiconductor fin comprising:
 a plurality of vertically stacked semiconductor patterns, every other semiconductor pattern of the plurality of vertically stacked semiconductor patterns including two portions horizontally spaced apart.   
     
     
         23 . The semiconductor fin of  claim 22 , wherein at least one of the plurality of vertically stacked semiconductor patterns has a rounded periphery.