Semiconductor integrated circuit

Abstract

Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. Since the self-test part has plural test sequencers corresponding to plural test modes, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs.

1 . A synchronous DRAM, comprising:
 a memory core which includes a plurality of memory banks having plural dynamic memory cells arrayed in a matrix, the memory banks accessed by specifying access addresses, each of the access addresses including one of bank addresses, one of X addresses and one of Y addresses;   an interface circuit configured to receive an external control signal, address signals, an external clock signal, and a clock enable signal from an outside of the synchronous DRAM and provide a test enable signal, an internal control signal, internal address signals, and the external clock signal, the external clock signal being captured in response to the clock enable signal; and   a built-in tester configured to test the memory core in response to the test enable signal, the internal control signal, the internal address signals, and the external clock signal from the interface circuit and generate test control codes for the memory core and the access addresses,   wherein the built-in tester comprises   a test controller configured to receive the test enable signal, the internal control signals, the internal address signals, and the external clock signal and generate select signals as test sequence commands that instruct test sequences, and   a plurality of test sequencers each of which corresponds to each of the test sequences and is selected in response to the select signals,   wherein test sequences differ in a manner of scanning at least one of the X addresses, the Y addresses, and the bank access addresses, and   wherein the built-in tester includes a clock generating circuit configured to receive the external clock signal from the interface circuit and provide an internal clock signal for a test supplied to the memory core, and a frequency of the internal clock signal is controlled by the test controller.   
     
     
         2 . A synchronous DRAM according to  claim 1 ,
 wherein the clock generating circuit comprises   a ring oscillator configured to change a number of gate stages of an oscillation loop, changeable frequency dividers configured to frequency-divide an output of the ring oscillator at a different frequency division ratio and output a plurality of clock signals, selectors configured to select the plurality of clock signals from the changeable frequency dividers, and   an oscillation frequency control circuit configured to control a number of gate stages of the oscillation loop based on comparison between a predetermined output of the changeable frequency dividers and an external clock signal.