Angled implantation for removal of thin film layers

Abstract

Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

1 . A semiconductor device, comprising:
 a substrate;   a gate dielectric layer on the substrate, the gate dielectric layer having a length;   a gate electrode on the gate dielectric layer, the gate electrode having a gate length adjacent the gate dielectric layer, the gate electrode having reverse-tapered sidewalls so the gate electrode has an intermediate length further from the gate dielectric layer than the gate length, the intermediate length being greater than the gate length; and   wherein the length of the gate dielectric layer is between about 120% and about 85% of the gate length.   
   
   
       2 . The device of  claim 1 , wherein at least a portion of the gate electrode sidewalls has a sidewall angle between the gate electrode sidewalls and a top surface of the substrate, the sidewall angle being between about eighty-five degrees and about seventy-five degrees. 
   
   
       3 . The device of  claim 1 , wherein the gate electrode includes a work function metal gate layer comprising a first metal and a second metal gate layer comprising a second metal different than the first metal on the work function metal gate layer. 
   
   
       4 . The device of  claim 3 , wherein the work function metal gate layer is conformal to the bottom and sidewalls and has a thickness between about 50 angstroms and about 100 angstroms. 
   
   
       5 . The device of  claim 1 , wherein the length of the gate dielectric layer is between about 105% and about 97% of the gate length. 
   
   
       6 . The device of  claim 1 , wherein the gate length is between about 18 nanometers and about 22 nanometers and the length of the gate dielectric layer is between about 23.2 nanometers and about 17.4 nanometers. 
   
   
       7 . The device of  claim 1 , wherein the gate dielectric layer has a footing less than or equal to about six angstroms on each side. 
   
   
       8 . The device of  claim 1 , wherein the gate dielectric layer has an undercut less than or equal to about three angstroms on each side.