Cmos varactor

Abstract

A varactor and method of fabricating the varactor. The varactor includes a silicon body in a silicon layer of an SOI substrate; a polysilicon electrode comprising a gate region and a plate region separated from the body by a gate dielectric layer, the gate and plate regions contiguous, the electrode electrically connected to a first pad; and a source formed in the body on a first side of the gate region, a drain formed in the body on a second and opposite side of the gate region, and a body contact formed in the body on a side of the plate region away from the gate region, the source, drain and body contact, separated from each other by regions of the body under the electrode, the source, drain and body contact electrically connected to each other and to a second pad.

1 . A varactor, comprising:
 a substrate comprising a single-crystal upper silicon layer separated from a lower silicon layer by a buried oxide layer;   dielectric isolation abutting sidewalls of a region of said upper silicon layer and thereby defining a body in said upper silicon layer, said dielectric isolation extending from a top surface of said substrate to a top surface of said buried oxide layer;   a polysilicon electrode comprising a gate region and a plate region separated from said body by a gate dielectric layer, said gate and plate regions contiguous, said electrode electrically connected to a first pad; and   a source formed in said body on a first side of said gate region, a drain formed in said body on a second and opposite side of said gate region, and a body contact formed in said body on a side of said plate region away from said gate region, said source, drain and body contact, separated from each other by regions of said body under said electrode, said source, drain and body contact electrically connected to each other and to a second pad.   
   
   
       2 . The varactor of  claim 1 , wherein a maximum capacitance of said varactor is a function of an area of said plate region and a minimum capacitance of said varactor is substantially insensitive to said area of said plate region. 
   
   
       3 . The varactor of  claim 1 , wherein said source, said drain, said gate region and a first region of said plate region are doped N-type and said body, said body contact and a second region of said plate region are doped P-type, a doping level of said body at least an order of magnitude less than a doping level of said body contact or a doping level of said source and said drain. 
   
   
       4 . The varactor of  claim 1 , wherein said source, said drain, said gate region and a first region of said plate region are doped P-type and said body, said body contact and a second region of said plate region are doped N-type, a doping level of said body at least an order of magnitude less than a doping level of said body contact or a doping level of said source and said drain. 
   
   
       5 . The varactor of  claim 1 , wherein:
 said body has first and second sidewalls parallel to said first and second sides of said gate region and opposite first and second ends, said source and said drain extend along opposite sidewalls of said body and abutting said first end of said body, said body contact extending along said second end of said body and abutting said first and second sides of said body.   
   
   
       6 . The varactor of  claim 5 , wherein:
 said electrode comprises a first region having a first major axis parallel to said first and second sides of said gate region, a second region having a second major axis and a third region having a third major axis, said second and third major axes perpendicular to said first major axis, said first, second, and third regions contiguous, said second region intervening between said first and third regions, said gate region comprising said first region and said plate region comprising said second and third regions.   
   
   
       7 . The varactor of  claim 6 , wherein a maximum capacitance of said varactor is a function of an area of said second region and substantially insensitive to an area of said third region and a minimum capacitance of said varactor is substantially insensitive to said areas of said second and third regions. 
   
   
       8 . A method of fabricating a varactor, comprising:
 forming dielectric isolation abutting sidewalls of a region of a single crystal upper silicon layer of a substrate and thereby defining a body in said upper silicon layer, said substrate comprising said upper silicon layer separated from a lower silicon layer by a buried oxide layer, said dielectric isolation extending from a top surface of said substrate to a top surface of said buried oxide layer;   forming a polysilicon electrode comprising a gate region and a plate region separated from said body by a gate dielectric layer, said gate and plate regions contiguous;   electrically connecting said electrode to a first pad;   forming a source in said body on a first side of said gate region, a drain in said body on a second and opposite side of said gate region, and a body contact in said body on a side of said plate region away from said gate region, said source, drain and body contact, separated from each other by regions of said body under said electrode; and   electrically connecting said source, drain and body contact to each other and to a second pad.   
   
   
       9 . The method of  claim 8 , wherein a maximum capacitance of said varactor is a function of an area of said plate region and a minimum capacitance of said varactor is substantially insensitive to said area of said plate region. 
   
   
       10 . The method of  claim 8 , further including:
 simultaneously doping said source, drain, said gate region and a first region of said plate region N-type and simultaneously doping said body, said body contact and a second region of said plate region P-type, a doping level of said body at least an order of magnitude less than a doping level of said body contact or a doping level of said source and said drain.   
   
   
       11 . The method of  claim 8 , further including:
 simultaneously doping said source, drain and a first region of said gate region P-type; and;   simultaneously doping said body, said body contact, said plate region and a second region of said plate region N-type, a doping level of said body at least an order of magnitude less than a doping level of said body contact or a doping level of said source and said drain.   
   
   
       12 . The method of  claim 8 , wherein:
 said body has first and second sidewalls parallel to said first and second sides of said gate region and opposite first and second ends, said source and said drain extend along opposite sidewalls of said body and abutting said first end of said body, said body contact extending along said second end of said body and abutting said first and second sides of said body.   
   
   
       13 . The varactor of  claim 12 , wherein:
 said electrode comprises a first region having a first major axis parallel to said first and second sides of said gate region, a second region having a second major axis and a third region having a third major axis, said second and third major axes perpendicular to said first major axis, said first, second, and third regions contiguous, said second region intervening between said first and third regions, said gate region comprising said first region and said plate region comprising said second and third regions.   
   
   
       14 . The varactor of  claim 13 , wherein a maximum capacitance of said varactor is a function of an area of said second region and substantially insensitive to an area of said third region and a minimum capacitance of said varactor is substantially insensitive to said areas of said second and third regions.