Production method for wiring and vias

Abstract

It is an object of the present invention to alleviate a work for removing an unnecessary metal layer when wiring and vias are formed on a substrate by electroplating. An additive is added to a plating solution to be used for electroplating. The additive has a plating reaction suppressing capability, but has a characteristic that the plating reaction suppressing capability is reduced as the plating reaction progresses. The additive has a capability for increasing a metal deposition overpotential and has a characteristic that the metal deposition overpotential is reduced as the reaction progresses. As a result, the metal can be deposited selectively in a trench and a via formed on the substrate. When a wiring and a via are formed on the substrate, the trench and the via having a predetermined surface roughness are formed on the substrate.

1 . A production method for wiring and vias, comprising:
 trenches and vias forming step for forming trenches corresponding to a wiring on a surface of a substrate and forming a vias on a position where the via holes should be formed;   a seed layer forming step for forming a first metal layer as a seed layer for electroplating on the substrate surface with the trench and the via formed thereon; and an electroplating step for forming a second metal layer in the trench and the via by electroplating,   wherein an additive, which has a plating reaction suppressing capability and a characteristic such that the plating reaction suppressing capability is reduced as the plating reaction progresses, is added to a plating solution to be used at the electroplating step.   
   
   
       2 . The production method for wiring and vias according to  claim 1 , wherein the additive contains at least one of cyanine dye and its derivatives which are expressed by the following formula: 
     
       
         
         
             
             
         
       
     
     where n is any one of 0, 1, 2 and 3. 
   
   
       3 . The production method for wiring and vias according to  claim 1 , wherein the additive has a capability for increasing a metal deposition overpotential. 
   
   
       4 . The production method for wiring and vias according to  claim 1 , wherein the plating solution has a characteristic that when a polarization curve representing a relationship between an electric potential of a disk electrode and a current density is obtained per rotational speed of the disk electrode, the current density at the time when the rotational speed of the disk electrode is 1000 rpm is lower than the current density at the time when the rotational speed of the disk electrode is zero in an area of a first electric potential, and the current density at the time when the rotational speed of the disk electrode is 1000 rpm is higher than the current density at the time when the rotational speed of the disk electrode is zero in an area of a second applied potential which is more negative than the first electric potential. 
   
   
       5 . The production method for wiring and vias according to  claim 1 , wherein the plating solution has a characteristic that when a polarization curve representing a relationship between an electric potential of a disk electrode and a current density is obtained per rotational speed of the disk electrode, the current density at the time when the rotational speed of the disk electrode is 1000 rpm is not more than 1/10 0  of the current density at the time when the rotational speed of the disk electrode is zero in a range where the electric potential is +100 to 200 mV with respect to a standard hydrogen electrode potential, and the current density at the time when the rotational speed of the disk electrode is 1000 rpm is higher than the current density at the time when the rotational speed of the disk electrode is zero in a range where the electric potential is more negative than −100 mV with respect to the standard hydrogen electrode potential. 
   
   
       6 . The production method for wiring and vias according to  claim 1 , wherein the plating solution is an acid copper sulfate solution, and the second metal layer is made by copper. 
   
   
       7 . The production method for wiring and vias according to  claim 1 , wherein the first metal layer is formed by copper, nickel, cobalt, chromium, tungsten, palladium and titanium, or nickel, cobalt, chromium, tungsten, palladium and titanium, or alloy which contains at least one of them. 
   
   
       8 . The production method for wiring and vias according to  claim 1 , wherein only the trench and the via are subject to surface roughening treatment. 
   
   
       9 . The production method for wiring and vias according to  claim 1 , wherein after the seed layer forming step and before the electroplating step, arithmetic average roughness Ra defined by JISB0601 in the trench and the via is larger than arithmetic average roughness Ra defined by JISB0601 on areas other than the trench and the via. 
   
   
       10 . The production method for wiring and vias according to  claim 1 , wherein after the seed layer forming step and before the electroplating step, an average length RSm of a roughness curvilinear element defined by JISB0601 in the trench and the via is smaller than an average length RSm of a roughness curvilinear element defined by JISB0601 on areas other than the trench and the via. 
   
   
       11 . The production method for wiring and vias according to  claim 1 , wherein after the seed layer forming step and before the electroplating step, arithmetic average roughness Ra defined by JISB0601 in the trench and the via is not less than 10 times as large as arithmetic average roughness Ra defined by JISB0601 on areas other than the trench and the via, and an average length RSm of a roughness curvilinear element defined by JISB0601 in the trench and the via is not more than 1/10 times as large as an average length RSm of a roughness curvilinear element defined by JISB0601 on areas other than the trench and the via. 
   
   
       12 . The production method for wiring and vias according to  claim 1 , wherein after the seed layer forming step and before the electroplating step, arithmetic average roughness Ra defined by JISB0601 in the trench and the via is 0.01 to 4 μm, and an average length RSm of a roughness curvilinear element defined by JISB0601 in the trench and the via is 0.005 to 8 μm. 
   
   
       13 . The production method for wiring and vias according to  claim 1 , wherein at the trench and the via forming step, the trench and the via are formed simultaneously on the substrate. 
   
   
       14 . The production method for wiring and vias according to  claim 1 , wherein the trench and the via are formed by any one of a photolithography method, a laser radiation method and a nanoimprint method.