Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search

Abstract

A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.

1 . A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions, the method comprising:
 partitioning the plurality of physical register files into a first set of register files having a fixed one-to-one mapping with a first set of logical registers in the architected state and into a second set of register files being mapped to a second set having multiple copies of logical registers in a non-architected state by a register-renaming unit;   assigning an instruction tag to each of the plurality of instructions for tracking instruction dependencies;   using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register;   using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads;   using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and   performing the register renaming scheme at an instruction dispatch or wake-up/issue time in order to reduce a number of the plurality of physical register files.   
   
   
       2 . The method of  claim 1 , wherein the register-renaming unit is a mapper. 
   
   
       3 . The method of  claim 2 , wherein the mapper maps the first set of logical registers to a plurality of physical registers in a rename registerfile and maintains a copy of previous instruction dependency information for a flush/recovery function. 
   
   
       4 . A system for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions, the system comprising:
 a network; and   a host system in communication with the network, the host system including software to implement a method comprising:
 partitioning the plurality of physical register files into a first set of register files having a fixed one-to-one mapping with a first set of logical registers in the architected state and into a second set of register files being mapped to a second set having multiple copies of logical registers in a non-architected state by a register-renaming unit; 
 assigning an instruction tag to each of the plurality of instructions for tracking instruction dependencies; 
 using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; 
 using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; 
 using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and 
 performing the register renaming scheme at an instruction dispatch or wake-up/issue time in order to reduce a number of the plurality of physical register files. 
   
   
   
       5 . The system of  claim 4 , wherein the register-renaming unit is a mapper. 
   
   
       6 . The system of  claim 5 , wherein the mapper maps the first set of logical registers to a plurality of physical registers in a rename registerfile and maintains a copy of previous instruction dependency information for a flush/recovery function. 
   
   
       7 . The system of  claim 6 , wherein the plurality of physical registers used by in-flight instructions are mapped to either the first set of logical registers in architected state or to the second set of logical registers in a non-architected state.