Nonvolatile Semiconductor Memory Device

Abstract

A nonvolatile semiconductor memory device capable of suppressing parasitic currents in unselected memory cells, in cross-point array including memory cells comprising a two-terminal circuit having a variable resistor storing information according to electric resistance change due to electric stress. The memory cell comprises a series circuit of the variable resistive element holding a variable resistor between an upper and lower electrodes, and the two-terminal element having non-linear current-voltage characteristics making currents flow bi-directionally. The two-terminal element has a switching characteristic that currents bi-directionally flow according to polarity of a voltage applied to both ends when an absolute voltage value exceeds a certain value, and currents larger than predetermined minute currents do not flow when the absolute value is the certain value or less, and can make currents whose current density is 30 kA/cm 2 or more flow regularly when a predetermined high voltage whose absolute value exceeds the certain value is applied.

1 . A nonvolatile semiconductor memory device comprising:
 a memory cell array with a plurality of memory cells arranged in a row direction and in a column direction, each of the memory cells comprising a two-terminal circuit having a variable resistor for storing information in accordance with a change of an electric resistance due to electric stress, wherein   the memory cells have switching characteristics that currents bi-directionally flow according to voltage polarity of a voltage applied to both ends of the memory cells when an absolute value of the voltage exceeds a certain value, and currents larger than predetermined minute currents do not flow when the absolute value of the applied voltage is the certain value or less, and can make currents whose current density is 30 kA/cm 2  or more flow regularly when a predetermined high voltage whose absolute value exceeds the certain value is applied.   
     
     
         2 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the memory cell comprises a variable resistive element in which a variable resistor is held between an upper electrode and a lower electrode, and a two-terminal element connected to the variable resistive element in series and having non-linear current-voltage characteristics allowing currents to flow bi-directionally, wherein   the two-terminal element has switching characteristics that currents bi-directionally flow according to voltage polarity of a voltage applied to both ends of the two-terminal element when an absolute value of the voltage exceeds a certain value, and currents larger than predetermined minute currents do not flow when the absolute value of the applied voltage is the certain value or less, and can make currents whose current density is 30 kA/cm 2  or more flow regularly when a predetermined high voltage whose absolute value exceeds the certain value is applied.   
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 2 , wherein the two-terminal element is a varistor. 
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 2 , wherein the two-terminal element is mainly composed of zinc oxide or SrTiO 3 . 
     
     
         5 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the lower electrode of the plurality of memory cells arranged in the same row is connected to a common word line, the upper electrode of the plurality of memory cells arranged in the same column is connected to a common bit line in the memory cell array, and the nonvolatile semiconductor memory device at least comprising:   a control circuit for controlling programming, erasing, and reading of information into/from the memory cells;   a voltage switch circuit for switching a programming voltage, an erasing voltage, and a reading voltage to be applied to the word line and the bit line; and   a reading circuit for reading the information from the memory cells.   
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 1 , wherein the polarity of the voltage applied to the memory cell is inverted in programming and in erasing. 
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 1 , wherein the variable resistor is a metal oxide having a perovskite type crystalline structure. 
     
     
         8 . The nonvolatile semiconductor memory device according to  claim 1 , wherein the variable resistor is a metal oxide expressed by a general formula, Pr 1−x Ca x MnO 3  (X=0.3, 0.5).