High frequency delay circuit and test apparatus

Abstract

A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal.

1 .- 10 . (canceled) 
   
   
       11 . A test apparatus operable to test an electronic device, comprising:
 a pattern generator operable to generate a test pattern for testing the electronic device;   a high frequency delay circuit operable to generate a high frequency clock, of which a frequency is higher than the reference clock, and of which a phase is delayed for a desired delay time, based on the supplied reference clock; and   a wave shaping section operable to form the test pattern according to the high frequency clock, and to supply it to the electronic device, wherein said high frequency delay circuit comprises: a variable delay circuit operable to receive the reference clock and to output a delay clock delayed from the reference clock for the desired delay time in advance; and   a multiplier operable to generate the high frequency clock, of which a frequency is a frequency of the delay clock multiplied by a predetermined value, and to output the generated high frequency clock at timing according to a phase of the delay clock.   
   
   
       12 . The test apparatus as claimed in  claim 11 , wherein a plurality of said high frequency delay circuits are provided according to a plurality of pins of the electronic device to which the test pattern is to be supplied, and the test apparatus further comprises a jitter reduction circuit operable to reduce a jitter of the reference clock and to supply it to said plurality of high frequency delay circuits. 
   
   
       13 . (canceled)