Stressed mos device and methods for its fabrication

Abstract

Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width.

1 . An MOS transistor comprising:
 a monocrystalline semiconductor substrate;   a gate insulator overlying the monocrystalline semiconductor substrate;   a polycrystalline silicon gate electrode overlying the gate insulator, the polycrystalline silicon gate electrode comprising a first portion having a first width in contact with the gate insulator and extending upwardly away from the gate insulator to a second portion having a second width greater than the first width; and   a tensile stressed film overlying the second portion.   
     
     
         2 . The MOS transistor of  claim 1  further comprising a spacer material adjacent the first portion beneath the second portion, the spacer material having a Young's modulus significantly less than the Young's modulus of the polycrystalline silicon forming the polycrystalline silicon gate electrode. 
     
     
         3 . The MOS transistor of  claim 2  wherein the spacer material comprises silicon oxide and the tensile stressed film comprises silicon nitride. 
     
     
         4 . The MOS transistor of  claim 2  wherein the spacer material further comprises a layer of tensile stressed material. 
     
     
         5 . The MOS transistor of  claim 4  wherein the tensile stressed material comprises silicon nitride. 
     
     
         6 . The MOS transistor of  claim 1  wherein the monocrystalline semiconductor substrate comprises a silicon substrate having a surface oriented in the (100) crystalline plane. 
     
     
         7 . The MOS transistor of  claim 6  wherein the first portion overlies a channel in the silicon substrate and the channel has a longitudinal direction oriented along the [110] crystal direction. 
     
     
         8 . An MOS transistor comprising:
 a monocrystalline semiconductor substrate;   a T-shaped gate electrode formed of a material having a first Young's modulus overlying the monocrystalline semiconductor substrate, the T-shaped gate electrode having a first vertical portion having a first width and a second horizontal portion having a second width greater than the first width and overhanging a space beneath the second horizontal portion and adjacent the first vertical portion;   a tensile stressed film overlying the second horizontal portion; and   an insulating material comprising a material having a second Young's modulus less than the first Young's modulus in the space beneath the second horizontal portion.   
     
     
         9 . The MOS transistor of  claim 8  wherein the insulating material further comprises a layer of tensile stressed material. 
     
     
         10 . The MOS transistor of  claim 8  wherein the monocrystalline semiconductor substrate comprises a silicon substrate having a surface oriented in the (100) crystalline plane. 
     
     
         11 . The MOS transistor of  claim 10  wherein the first vertical portion overlies a channel in the silicon substrate and the channel has a longitudinal direction oriented along the [110] crystal direction. 
     
     
         12 . The MOS transistor of  claim 1 , wherein the first portion has a thickness of about 100 nm. 
     
     
         13 . The MOS transistor of  claim 1 , further comprising a thin layer of silicon oxide disposed adjacent sidewalls of the first portion of the polycrystalline silicon gate electrode. 
     
     
         14 . The MOS transistor of  claim 1 , wherein the second portion is centered over the first portion. 
     
     
         15 . The MOS transistor of  claim 2 , wherein the spacer material comprises silicon oxide, silica glass doped with phosphorous, silica glass doped with boron, silica glass doped with phosphorous and boron, or porous dielectric materials. 
     
     
         16 . The MOS transistor of  claim 2 , further comprising sidewall spacers interposed between sidewalls of the first portion of the polycrystalline silicon gate electrode and the spacer material, wherein the sidewall spacers are formed of a material having a high tensile stress. 
     
     
         17 . The MOS transistor of  claim 16 , wherein the sidewall spacers comprise silicon nitride. 
     
     
         18 . The MOS transistor of  claim 8 , further comprising sidewall spacers interposed between sidewalls of the first vertical portion of the T-shaped gate electrode and the insulating material, wherein the sidewall spacers are formed of a material having a high tensile stress. 
     
     
         19 . The MOS transistor of  claim 18 , wherein the sidewall spacers comprise silicon nitride. 
     
     
         20 . The MOS transistor of  claim 8 , wherein the insulating material comprises silicon oxide, silica glass doped with phosphorous, silica glass doped with boron, silica glass doped with phosphorous and boron, or porous dielectric materials.