Chip on film (cof) package having test pad for testing electrical function of chip and method for manufacturing same

Abstract

A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip.

1 . A chip on film (COF) package comprising a semiconductor chip mounted on a base film, the COF package comprising:
 a signal-input portion for receiving data and control signals and for transmitting the data and the control signals to the semiconductor chip;   a plurality of passive elements connected to terminals of the semiconductor chip; and   a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion.   
   
   
       2 . The COF package of  claim 1 , wherein each of the test pads comprises a first solder pattern connected to a terminal of the semiconductor chip, and a second solder pattern connected to another terminal of the semiconductor chip. 
   
   
       3 . The COF package of  claim 2 , wherein the first and second solder patterns comprise protrusion patterns formed between the first and second solder patterns. 
   
   
       4 . The COF package of  claim 3 , wherein the protrusion patterns of the first and second solder patterns are used to connect the first and second solder patterns. 
   
   
       5 . The COF package of  claim 2 , wherein the test pads further comprise a dedicated test pad which is separately formed from other test pads for testing a terminal of the semiconductor chip. 
   
   
       6 . The COF package of  claim 1 , wherein the test pads comprise:
 a first test pad comprising a first solder pattern connected to a terminal of the semiconductor chip and a second solder pattern connected to another terminal of the semiconductor chip; and   a second test pad separately formed from the first test pad and connected to another terminal of the semiconductor chip.   
   
   
       7 . The COF package of  claim 1 , wherein the semiconductor chip comprises a liquid crystal device (LCD) driver chip for driving an external LCD. 
   
   
       8 . The COF package of  claim 7 , wherein the test pads comprise first and second solder patterns connected to a supply voltage terminal and a clock enable terminal of the semiconductor chip, respectively, wherein the first and second solder patterns are short-circuited after testing the electrical function of the supply voltage terminal and the clock enable terminal of the semiconductor chip. 
   
   
       9 . A method for manufacturing a chip on film (COF) package comprising a semiconductor chip mounted on a base film, the method comprising the steps of:
 forming a pad for mounting passive elements and forming at least one test pad during patterning the base film, wherein the test pad comprises a plurality of patterns connected to different terminals of the semiconductor chip;   bonding the semiconductor chip to an inner lead formed on the base film;   testing each terminal connected to the test pad;   coating the pad for mounting the passive element and the test pad with a solder paste after completing the testing of the terminals connected to the test pad;   aligning and joining the passive element on a predetermined pad; and   heating the test pad to short-circuit the patterns.   
   
   
       10 . The method of  claim 9 , wherein the step of forming the pad for mounting passive elements and forming at least one test pad during patterning the base film comprises the step of forming a first solder pattern of the test pad connected to a terminal of the semiconductor chip and a second solder pattern of the test pad connected to another terminal of the semiconductor chip. 
   
   
       11 . The method of  claim 10 , wherein the step of forming the pad for mounting passive elements and forming at least one test pad during patterning the base film further comprises the step of forming a protrusion pattern of the test pad, wherein the protrusion pattern comprises a plurality of protrusion portions alternately connected to the other sides of the first and second solder patterns, respectively. 
   
   
       12 . A chip on film (COF) package comprising a semiconductor chip mounted on a base film, the COF package comprising:
 a connector comprising a plurality of terminals connected to terminals of the semiconductor device; and   a plurality of test pads, internally formed in the COF package, for testing terminals of the semiconductor device that are not connected to the connector.   
   
   
       13 . The COF package of  claim 12 , wherein the test pads comprise:
 a common test pad comprising a first solder pattern connected to a terminal of the semiconductor chip and a second solder pattern connected to another terminal of the semiconductor chip; and   a dedicated test pad separately formed from the common test pad and connected to another terminal of the semiconductor chip.   
   
   
       14 . The COF package of  claim 13 , wherein the first and second solder patterns of the common test pad comprise protrusion patterns formed between the first and second solder patterns. 
   
   
       15 . The COF package of  claim 14 , wherein the protrusion patterns of the first and second solder patterns are used to connect the first and second solder patterns, after testing the terminals of the semiconductor device connected to the first and second solder patterns.