Semiconductor package and manufacturing method therefor

Abstract

A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12 , and an IC chip, mounted on the obverse face of the multilayer wiring board 12 , and multiple bump terminals 16 , mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40 . The end faces of the conductive coatings 44 appear like rings around the insulating cores 42 , and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12 . Vias 36 are arranged immediately above the bump terminals 16 , and clearance holes 34 , the diameter of which is smaller than the diameter of the bump terminals 16 , are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

1 - 6 . (canceled) 
     
     
         7 . A manufacturing method for a semiconductor package including a printed wiring board and an integrated circuit chip mounted on an obverse face of said printed wiring board, comprising the steps of:
 preparing said printed wiring board; and   preparing a plurality of bump terminals, each including an insulating core, having a flat face to be directed toward the reverse face of said printed wiring board, and a conductive coating, formed on the outer surface of said bump terminal, except for the flat face of said insulating core; and   the printed wiring board includes:
 an insulating board; 
 an annular joint pad formed on the reverse face of the insulating board, and joined with an annular end surface of the conductive coating to be appeared around the flat face of the bump terminal; 
 an internal wiring pattern buried in the insulating board, and having a clearance hole smaller than the size of the flat face of the insulating core; 
 via lands arranged on the annular joint pad or within the joint pad, and electrically connected to the annular connected pad; and 
 vias located on the via land, and penetrating through the clearance hole; and 
   the manufacturing method further comprises the step of:
 joining the annular end surface of the conductive coating to be appeared around the flat face of the plurality of bump terminals.