Level shifter and semiconductor device having off-chip driver

Abstract

Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

1 . A level shifter comprising:
 a boost logic element receiving an input signal at a level of the first power supply voltage and an intermediate power supply voltage, and generating an output signal;   an output logic element receiving a second power supply voltage and the output of the boost logic element, and generating an output signal at a level of the second power supply voltage;   wherein the level of the intermediate power supply voltage is between the level of the first power supply voltage and the level of the second power supply voltage.   
   
   
       2 . The level shifter of  claim 1 , wherein the boost logic element comprises a boost inverter comprising a first PMOS transistor and a first NMOS transistor series connected between the intermediate power supply voltage and ground, and the gates of the first PMOS and NMOS transistors commonly receive the input signal and the output signal of the boost inverter is provided at a voltage node between the first PMOS and NMOS transistors. 
   
   
       3 . The level shifter of  claim 2 , wherein the output logic element comprises an output inverter comprising a second PMOS transistor and a second NMOS transistor series connected between the second power supply voltage and ground, and the gates of the second PMOS and NMOS transistors commonly receive the output signal of the boost inverter and the output signal is provided at a voltage node between the second PMOS and NMOS transistors. 
   
   
       4 . The level shifter of  claim 1 , wherein the boost logic element and the output logic element are implemented using a plurality of inverters, a plurality of NAND gates, or a plurality of NOR gates. 
   
   
       5 . A level shifter comprising:
 a boost logic element receiving an input signal at a level of the first power supply voltage and a first intermediate power supply voltage, and generating an output signal;   an auxiliary logic element receiving the output signal of the boost logic element and a second intermediate power supply voltage, and generating an output signal; and   an output logic element receiving the output of the auxiliary logic element and a second power supply voltage, and generating an output signal;   wherein the respective levels of the first and second intermediate power supply voltages are between the level of the first power supply voltage and the level of the second power supply voltage.   
   
   
       6 . The level shifter of  claim 5 , wherein the first and second intermediate power supply voltages have the same level, 
   
   
       7 . The level shifter of  claim 5 , wherein the second intermediate power supply voltage is higher than the first intermediate power supply voltage. 
   
   
       8 . The level shifter of  claim 5 , wherein the boost logic element comprises a boost inverter comprising a first PMOS transistor and a first NMOS transistor series connected between the first intermediate power supply voltage and ground, and the gates of the first PMOS and NMOS transistors commonly receive the input signal and the output signal of the boost inverter is provided at a voltage node between the first PMOS and NMOS transistors. 
   
   
       9 . The level shifter of  claim 8 , wherein the auxiliary logic element comprises an auxiliary inverter comprising a second PMOS transistor and a second NMOS transistor series connected between the second intermediate power supply voltage and ground, and the gates of the second PMOS and NMOS transistors commonly receive the output signal of the boost inverter and the output signal of the auxiliary inverter is provided at a voltage node between the second PMOS and NMOS transistors. 
   
   
       10 . The level shifter of  claim 9 , wherein the output logic element comprises an output inverter comprising a third PMOS transistor and a third NMOS transistor series connected between the second power supply voltage and ground, and the gates of the third PMOS and NMOS transistors commonly receive the output signal of the auxiliary inverter and the output signal is provided at a voltage node between the third PMOS and NMOS transistors. 
   
   
       11 . A semiconductor device comprising an OFF-chip driver (OCD), comprising:
 a pull-up level shifter generating a level-shifted, first-state, data pull-up signal having a second power supply voltage level in response to first-state internal data having a first power supply voltage level, wherein the pull-up level shifter comprises a plurality of series connected pull-up logic gates receiving as power supply voltages at least one pull-up intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, the at least one pull-up intermediate power supply voltage of the pull-up logic gates having either a same voltage level or gradually increasing voltage levels;   a pull-up driver pulling up output data in response to the data pull-up signal and a pull-up control signal to output first-state output data having the second power supply voltage level.   
   
   
       12 . The device of  claim 11 , further comprising:
 a pull-down level shifter generating a level-shifted, first-state, data pull-down signal having a third power supply voltage level in response to the first-state internal data having the first power supply voltage level, the pull-down level shifter comprising a plurality of series connected pull-down logic gates receiving as power supply voltages at least one pull-down intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the third power supply voltage level, the at least one pull-down intermediate power supply voltage of the pull-down logic gates having either a same voltage level or gradually increasing voltage levels; and   a pull-down driver pulling down the output data in response to the data pull-down signal and a pull-down control signal to output second-state output data having a fourth power supply voltage level.   
   
   
       13 . The device of  claim 12 , further comprising:
 at least one up level shifter generating at least one level-shifted first-state data up signal having the third power supply voltage level in response to the first-state internal data having the first power supply voltage level, each up level shifter comprising a plurality of series connected logic gates receiving as power supply voltages at least one up intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the third power supply voltage level, the at least one up intermediate power supply voltage of the up logic gates having either a same voltage level or gradually increasing voltage level; and   an up driver controlling a voltage level of the first-state output data in response to the at least one data up signal and the at least one up control signal corresponding to the at least one data up signal   
   
   
       14 . The device of  claim 13 , further comprising:
 at least one down level shifter generating at least one level-shifted, first-state, data down signal having the third power supply voltage level in response to the first-state internal data having the first power supply voltage level, each down level shifter comprising a plurality of series connected down logic gates receiving as power supply voltages at least one down intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the third power supply voltage level, the at least one down intermediate power supply voltage of the down logic gates having either a same voltage level or gradually increasing voltage levels; and   a down driver controlling a voltage level of the second-state output data in response to the at least one data down signal and the at least one down control signal corresponding to the at least one data down signal.   
   
   
       15 . The device according to  claim 14 , wherein the pull-up, pull-down, up, and down level shifters further comprise a plurality of auxiliary logic gates respectively corresponding to the pull-up, pull-down, up, and down logic gates, each auxiliary logic gate interposed between two adjacent ones of the pull-up, pull-down, up, and down logic gates. 
   
   
       16 . The device according to  claim 15 , further comprising:
 a voltage regulator generating the pull-up, pull-down, up, and down intermediate power supply voltage.   
   
   
       17 . The device according to  claim 16 , further comprising:
 a pre-driver generating the pull-up control signal, the pull-down control signal, the at least one up control signal, and the at least one down control signal in response to the internal data to control impedance of the output data.