Delay calculation method capable of calculating delay time with small margin of error

Abstract

A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t 0, increases to V 1 during Δt 1; and the one indicating that the voltage increases from V 1 to E during Δt 2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of Δt 1, V 1, and Δt 2.

1 . A delay calculation method for a logic circuit including a MOS transistor,
 said transistor being modeled using a resistance element whose resistance value is fixed, and a power supply whose voltage varies with time,   a shape of a voltage waveform of said power supply being determined according to input waveform information that determines the shape of an input waveform inputted to said logic circuit.   
     
     
         2 . The delay calculation method according to  claim 1 , wherein
 said input waveform information includes:   information on potential of said input waveform at a time when a linear waveform that requires the same amount of time as said input waveform to transition between predetermined two potentials meets a power supply voltage or ground voltage which depends on whether said input waveform transitions from low to high or from high to low, respectively; and   information on time constant of an exponential waveform which passes through said potential of said input waveform at said time and a higher or lower one of said predetermined two potentials which depends on whether said input waveform transitions from low to high or from high to low, respectively.   
     
     
         3 . The delay calculation method according to  claim 1 , wherein
 operating characteristics of said transistor being modeled are represented as divided into a first region where current changes with changing gate potential, a second region where current decreases gradually while gate potential is constant, and a third region where current decreases while gate potential is constant,   said second region corresponding to a saturation region of said transistor,   said third region corresponding to a linear region of said transistor; and   when said transistor transitions from said first region to said second region and then to said third region, the shape of said voltage waveform of said power supply is determined according to said input waveform information.   
     
     
         4 . The delay calculation method according to  claim 3 , wherein
 a saturation current value of said transistor in said second region is calculated based on said input waveform information and is used to determine the shape of said voltage waveform of said power supply.   
     
     
         5 . The delay calculation method according to  claim 4 , wherein
 said saturation current value is calculated according to a mean gate potential of said transistor in said second region.