Semiconductor device and method for fabricating the same

Abstract

On an insulation layer 12 formed on a silicon substrate 10 , there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34 , a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34 , a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34 , a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.

1 . A semiconductor device comprising:
 an insulation layer formed on a substrate;   a silicon layer formed on the insulation layer;   a first transistor including a lattice-relaxed silicon germanium layer formed on the silicon layer in a first region, a tensile-strained silicon layer formed on the lattice-relaxed silicon germanium layer and a first gate electrode formed on the tensile-strained silicon layer with a first gate insulation film formed therebetween; and   a second transistor including a compression-strained silicon germanium layer formed on the silicon layer in a second region, and a second gate electrode formed on the compression-strained silicon germanium layer with a second gate insulation film formed therebetween.   
     
     
         2 . A semiconductor device according to  claim 1 , wherein
 a height of a surface of the silicon layer of the first transistor and a height of a surface of the silicon germanium layer of the second transistor are substantially equal to each other.   
     
     
         3 . A semiconductor device according to  claim 1 , wherein
 the first transistor is an NMOS transistor having the tensile-strained silicon layer as a channel, and   
     
     
         4 . A method for fabricating a semiconductor device comprising the steps of: forming a compression-strained silicon germanium layer on a silicon layer formed on a substrate with an insulation layer formed therebetween; and applying an energy beam to the compression-strained silicon germanium layer to lattice-relax the compression-strained silicon germanium layer; further comprising before the step of lattice-relaxing the compression-strained silicon germanium layer, the step of
 forming a cap layer of silicon on the compression-strained silicon germanium layer, and   in the step of lattice-relaxing the compression-strained silicon germanium layer, the energy beam being applied to the compression-strained silicon germanium layer through the cap layer.   
     
     
         5 . A method for fabricating a semiconductor device according to  claim 4 , wherein
 in the step of forming the cap layer, the cap layer is formed in a thickness of below 5 nm including 5 nm.