Semiconductor device, and method for manufacturing the same

Abstract

According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi 2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.

1 . A semiconductor device comprising:
 a N-channel MIS transistor comprising:
 a p-type semiconductor layer; 
 a first gate insulation layer formed on the p-type semiconductor layer; 
 a first gate electrode formed on the first gate insulation layer, the first gate electrode comprising a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms; and 
   a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length.   
   
   
       2 . A semiconductor device comprising:
 a substrate;   an N-channel MIS transistor comprising:
 a p-type semiconductor layer formed on the substrate; 
 a first gate insulation layer formed on the p-type semiconductor layer; 
 a first gate electrode formed on the first gate insulation layer, the first gate electrode comprising a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms; and 
 a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length; 
   a P-channel MIS transistor comprising:
 an n-type semiconductor layer formed on the substrate; 
 a second gate insulation layer formed on the n-type semiconductor layer; 
 a second gate electrode formed on the second gate insulation layer, the second gate electrode comprising a crystal phase including at least one of a cubic crystal of Ni3Si or a hexagonal crystal of Ni31Si12; and
 a second source-drain region formed in the n-type semiconductor layer where the second gate electrode sandwiched along a direction of gate length. 
 
   
   
   
       3 . The semiconductor device according to  claim 1 , wherein the crystal phase of cubic crystal of NiSi2 is polycrystal and a single phase. 
   
   
       4 . The semiconductor device according to  claim 1 , comprising;
 a first element segregation layer where at least one of a phosphor, arsenic, and antimony are segregated formed on a first-electrode-side of an interface between the first gate electrode and the first gate insulation layer; and   a second element segregation layer where a boron is segregated formed on second-gate-insulation-layer-side of an interface between the second gate electrode and the second gate insulation layer.   
   
   
       5 . The semiconductor device according to  claim 1 , wherein the first gate electrode comprises:
 an upper layer formed from a crystal phase including an orthorhombic crystal of TiSi2; and   a lower layer formed from the crystal phase including the cubic crystal of NiSi2.   
   
   
       6 . The semiconductor device according to  claim 5 , wherein the upper layer of the first gate electrode has a thickness of 4.6 nm to 24 nm. 
   
   
       7 . The semiconductor device according to  claim 1 , wherein the first gate electrode comprises:
 an upper layer formed from a crystal phase including an orthorhombic crystal of NiSi; and   a lower layer formed from the crystal phase including the cubic crystal of NiSi2.   
   
   
       8 . The semiconductor device according to  claim 1 , wherein the gate insulation layer has a layer including Hf. 
   
   
       9 . The semiconductor device according to  claim 1 , wherein the gate insulation layer has a layer formed from HfSiON. 
   
   
       10 . The semiconductor device according to  claim 2 , wherein the substrate is a bulk substrate. 
   
   
       11 .- 20 . (canceled)