Multithread processor

Abstract

To guarantee response time while strictly maintaining the priority specified by software, a processor ( 1 ) which is a multithread processor having a thread multiplexer ( 10 ), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is added to the instruction code, are supplied to the thread multiplexer. The issue information is valid from the second and subsequent instruction flows, and is saved temporarily in an issue information buffer. This issue information is for example the position of an operating cycle which can issue a high priority instruction, i.e., information showing a slot. The thread multiplexer issues a low priority instruction at another operating cycle at which a high priority instruction is not issued according to the issue information.

1 - 6 . (canceled) 
   
   
       7 . A processor which executes N (N is an integer equal to 2 or more) threads simultaneously or by time division without save and restore of a processor state;
 said thread has a priority; and   when N−1 or less threads are being executed, and a thread whose priority is higher than the threads being executed is received, termination processing of the threads whose priorities are lower than that of said thread is started, or said thread is executed as a low priority thread.   
   
   
       8 . (canceled) 
   
   
       9 . A processor which processes instruction execution by plural threads by selecting instructions to be issued by an issue instruction multiplexer; and
 said issue instruction multiplexer controls the positions of operating cycles at which instruction issue information in said issued instruction can be subsequently issued.   
   
   
       10 . A processor which executes N (N is an integer equal to 2 or more) threads simultaneously or by time division without save and restore of a processor state,
 wherein each of the threads has a priority,   wherein the processor executes N−1 or less first threads, and   wherein when the processor receives a second thread whose priority is higher than the first threads, the processor increases a number of the first threads by 1 and executes the second thread.   
   
   
       11 . The processor according to  claim 10 ,
 wherein when the processor receives the second thread, the processor starts an end processing of one of the first threads.   
   
   
       12 . The processor according to  claim 10 ,
 wherein the processor executes the second thread as a first priority thread, and   wherein the processor executes the first threads as second priority threads.   
   
   
       13 . The processor according to  claim 10 , further comprising:
 an instruction select circuit,   wherein the processor executes an instruction code decoded and supplied to the instruction select circuit,   wherein the instruction code comprises instruction issue information which is valid in a second cycle associated with a first cycle in which the instruction code is executing, and   wherein the instruction issue information indicates a position of a cycle which is able to execute the instruction code.