Semiconductor circuit, display apparatus employing the same, and driving method therefor

Abstract

Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

1 . A semiconductor circuit comprising:
 a first scanning circuit; and   a second scanning circuit;   each of the first and second scanning circuits including   a plurality of unit registers,   wherein an output of each of the unit registers of the first scanning circuit and an output of each of the unit registers of the second scanning circuit, corresponding to each other, are coupled to each other; and   each of the unit registers of the first and second scanning circuits includes   a circuit element that, responsive to a control signal supplied thereto, switches an output state of said each of the unit registers of the first and second scanning circuits between a state in which an output signal is output and a state in which no output signal is output.   
   
   
       2 . The semiconductor circuit according to  claim 1 , wherein, during the time one of the first and second scanning circuits is outputting an output signal, the other scanning circuit is in the state in which no output signal is output. 
   
   
       3 . The semiconductor circuit according to  claim 2 , wherein the scanning direction of the first scanning circuit is opposite to the scanning direction of the second scanning circuit. 
   
   
       4 . The semiconductor circuit according to  claim 3 , wherein the circuit element includes a first switch circuit and a second switch circuit,
 wherein the first and second switch circuits each are supplied with a signal specifying the scanning direction or a signal derived from the scanning direction specifying signal, as the control signal, so as to be thereby controlled on or off;   the first switch circuit is arranged between a gate electrode of a first output transistor in the unit register that outputs the output signal and a wiring that controls the gate electrode of the first output transistor; and   the second switch circuit is arranged between a node between the first switch circuit and the first output transistor and a signal line which is capable of turning off the first output transistor.   
   
   
       5 . The semiconductor circuit according to  claim 4 , wherein the circuit element further includes third and fourth switch circuits controlled by the signal specifying the scanning direction or the signal derived from the scanning direction specifying signal, as the control signal, so as to be thereby turned on or off,
 wherein the third switch circuit is arranged between a gate electrode of a second output transistor in the unit register that generates a control signal of a potential different from the potential of the first output transistor and a signal line controlling the gate electrode of the second output transistor; and   the fourth switch circuit is arranged between a connection node between the third switch circuit and the second output transistor and a signal line capable of turning off the second output transistor.   
   
   
       6 . The semiconductor circuit according to  claim 3 , wherein the circuit element includes:
 a first switch circuit and a second switch circuit, each being gate-controlled by a signal specifying the scanning direction or a signal derived from the scanning direction specifying signal;   a first output transistor and a second output transistor which generate the output signal;   a first signal line that is for turning off the first output transistor;   a second signal line that is for turning off the second output transistor; and   an output signal line for transferring an output signal of the unit register,   wherein the first switch circuit is arranged between the output signal line and the first control signal line; and   the second switch circuit is arranged between the output signal line and the second control signal line.   
   
   
       7 . The semiconductor circuit according to  claim 3 , wherein the circuit element includes:
 a switch circuit controlled on or off by a signal specifying the scanning direction or a signal derived from the scanning direction specifying signal;   an output signal line for transferring an output signal of the unit register;   an inverter circuit having an output connected to an output signal line and including two transistors of opposite conductivity types;   a high potential power supply line; and   a low potential power supply line,   wherein the switch circuit and the inverter circuit are arranged in series between the low potential power supply line and the high potential power supply line and the output signal line.   
   
   
       8 . The semiconductor circuit according to  claim 3 , wherein the circuit element includes:
 a first switch circuit and a second switch circuit, each being gate-controlled by a signal specifying the scanning direction or a signal derived from the scanning direction specifying signal;   an output signal line for transferring an output signal of the unit register,   an inverter circuit having an output connected to an output signal line and including two transistors of opposite conductivity types;   a high potential power supply line; and   a low potential power supply line,   wherein the first switch circuit is arranged between the low potential power supply line and the inverter circuit; and   the second switch circuit is arranged between the high potential power supply line and the inverter circuit.   
   
   
       9 . The semiconductor circuit according to  claim 3 , wherein the circuit element includes:
 a switch circuit controlled on or off by a signal specifying the scanning direction or a signal derived from the scanning direction specifying signal; and   a circuit that generates the output signal and that includes an inverter circuit including two transistors of opposite conductivity types,   wherein the switch circuit is arranged between the output signal line and an output node of the inverter circuit.   
   
   
       10 . The semiconductor circuit according to  claim 3 , wherein the unit register constituting the first scanning circuit and the unit register constituting the second scanning circuit are similar in circuit configuration and in circuit arrangement insofar as they affect the circuit operation. 
   
   
       11 . The semiconductor circuit according to  claim 3 , wherein each of the first and second scanning circuits is formed by NMOS transistors. 
   
   
       12 . The semiconductor circuit according to  claim 3 , wherein each of the first and second scanning circuits is formed by PMOS transistors. 
   
   
       13 . The semiconductor circuit according to  claim 3 , wherein each of the first and second scanning circuits is formed by a CMOS process. 
   
   
       14 . The semiconductor circuit according to  claim 3 , wherein the unit register includes:
 a first transistor having a gate and a drain connected to a second clock terminal;   a second transistor having a drain connected to a source of the first transistor, having a gate connected to an input terminal and having a source connected to a first power supply;   a third transistor having a gate and a drain connected to the input terminal;   a fourth transistor having a drain connected to a source of the third transistor, having a gate connected to the drain of the second transistor and having a source connected to the first power supply;   a fifth transistor having a drain connected to a first clock terminal, having a gate connected to a source of the third transistor and having a drain connected to an output terminal;   a sixth transistor having a drain connected to the output terminal and having a source connected to the first power supply;   a seventh transistor connected between a connection node between the source of the first transistor and the drain of the second transistor and a gate of the sixth transistor, and having a gate connected to a first control terminal; and   an eighth transistor having a drain connected to a gate of the sixth transistor, having a gate connected to a second control terminal and having a source connected to the first power supply.   
   
   
       15 . The semiconductor circuit according to  claim 14 , wherein the unit register is driven by three-phase clocks;
 a plurality of the unit registers, forming each scanning circuit, are connected in cascade;   a pulse delivered to the unit register of an initial stage is transferred to respective succeeding stage unit registers as the pulse phase is shifted from one unit register to the next;   two neighboring phases of the three-phase clock are supplied to the first and second clock terminals;   a pulse is supplied to an input signal terminal of the initial stage unit register;   an output terminal of each unit register is connected to an associated one of gate lines and connected to an input terminal of a trailing side unit register;   a signal that is activated for shifting in the forward direction and a signal that is activated for shifting in the reverse direction are supplied to the first and second control terminals of the unit register of the first scanning circuit; and   a signal that is activated for shifting in the reverse direction and a signal that is activated for shifting in the forward direction are supplied to the first and second control terminals of the unit register of the second scanning circuit.   
   
   
       16 . The semiconductor circuit according to  claim 3 , wherein the unit register includes:
 a first transistor having a drain and a gate connected to a second clock terminal;   a second transistor having a drain connected to a source of the first transistor, having a gate connected to an input terminal and having a source connected to a first power supply;   a third transistor having a drain and a gate connected to the input terminal;   a fourth transistor having a drain connected to a source of the third transistor, having a gate connected to a connection node between a source of the first transistor and a drain of the second transistor, and having a source connected to the first power supply;   a fifth transistor having a drain connected to a first clock terminal and having a source connected to an output terminal;   a sixth transistor having a drain connected to the output terminal and having a source connected to the first power supply;   a seventh transistor connected between a connection node between the source of the first transistor and the drain of the second transistor and a gate of the sixth transistor and having a gate connected to a first control terminal;   an eighth transistor connected between the gate of the sixth transistor and the first power supply and having a gate connected to a second control terminal;   a ninth transistor connected between a connection node between a source of the third transistor and a drain of the fourth transistor and a gate of the fifth transistor and having a gate connected to the first control terminal; and   a tenth transistor having a drain connected to a gate of the fifth transistor, having a source connected to the first power supply and having a gate connected to the second control terminal.   
   
   
       17 . The semiconductor circuit according to  claim 16 , wherein the unit register is driven by a three-phase clock;
 a plurality of the unit registers, forming each of the scanning circuits, are connected in cascade;   a pulse delivered to the unit register of the initial stage is transferred to respective succeeding stage unit registers as the pulse phase is shifted from one unit register to the next;   two neighboring phases of the three-phase clock are supplied to the first and second clock terminals;   a pulse is supplied to an input signal terminal of the initial stage unit register; an output terminal of the unit register is connected to an associated one of gate lines and connected to an input terminal of a succeeding stage unit register;   a signal that is activated for shifting in the forward direction and a signal that is activated for shifting in the reverse direction are supplied to the first and second control terminals of the unit register of the first scanning circuit, respectively; and   a signal that is activated for shifting in the reverse direction and a signal that is activated for shifting in the forward direction are supplied to the first and second control terminals of the unit register of the second scanning circuit, respectively.   
   
   
       18 . The semiconductor circuit according to  claim 3 , wherein the unit register includes:
 a first transistor having a drain and a gate connected to a second clock terminal;   a second transistor having a drain connected to a source of the first transistor, having a gate connected to an input terminal and having a source connected to a first power supply;   a third transistor having a drain and a gate connected to the input terminal,   a fourth transistor having a drain connected to a source of the third transistor, having a gate connected to a connection node between a source of the first transistor and a drain of the second transistor, and having a source connected to the first power supply;   a fifth transistor having a drain connected to a first clock terminal, and having a source connected to an output terminal;   a sixth transistor having a drain connected to the output terminal, and having a gate connected to a connection node between the source of the first transistor and the drain of the second transistor and a gate of the fourth transistor; and   a seventh transistor having a drain connected to a source of the sixth transistor, having a gate connected to a first control terminal and having a source connected to the first power supply.   
   
   
       19 . The semiconductor circuit according to  claim 18 , wherein the unit register is driven by a three-phase clock;
 a plurality of the unit registers, forming each scanning circuit, are connected in cascade; a pulse delivered to the unit register of the initial stage is transferred to respective trailing side stage unit registers as the pulse phase is shifted from one unit register to the next;   two neighboring phases of the three-phase clock are supplied to the first and second clock terminals;   a pulse is supplied to an input signal terminal of the initial stage unit register; an output terminal of each unit register is connected to an associated one of gate lines and connected to an input terminal of a trailing side unit register;   a signal that is activated for shifting in the forward direction is supplied to the first control terminal in the unit register of the first scanning circuit; and   a signal that is activated for shifting in the reverse direction is supplied to the first control terminal in the unit register of the second scanning circuit.   
   
   
       20 . The semiconductor circuit according to  claim 18 , wherein the unit register further includes an eighth transistor between the first clock terminal and the drain of the fifth transistor; the eighth transistor having a gate connected to the first control terminal. 
   
   
       21 . The semiconductor circuit according to  claim 3 , wherein the unit register includes:
 a latch circuit for latching an input signal in response to a clock signal; and   an output circuit for receiving an output of the latch circuit and having an output controlled on or off based on a first control signal.   
   
   
       22 . A display apparatus including:
 an array of a plurality of pixels; and   the semiconductor circuit according to  claim 1 , wherein the pixels are controlled by an output signal delivered from the unit register of the first scanning circuit or the second scanning circuit of the semiconductor circuit.   
   
   
       23 . The display apparatus according to  claim 22 , wherein the first scanning circuit and the second scanning circuit are opposingly and symmetrically arranged with the pixel array disposed therebetween. 
   
   
       24 . A method for driving a display apparatus including a first scanning circuit and a second scanning circuit arranged facing each other with a display section in-between for delivering a scanning signal from one line to another; the display part including an array of a plurality of pixels; the method comprising:
 setting the second scanning circuit in a state in which no output signal is output during when the first scanning circuit is outputting an output signal; and   setting the first scanning circuit in a state in which no output signal is output during when the second scanning circuit is outputting an output signal for a scan operation, a scanning direction of the second scanning circuit being opposite to a scanning direction of the first scanning circuit to perform bidirectional scanning.