Method and apparatus for a motion compensation instruction generator

Abstract

The present invention provides a method and an apparatus for an instruction generator that utilizes two or more parameters comprising one or more prediction mode parameters and one or more motion vector parameters to generate one or more motion compensation instructions for a prediction block in a macroblock.

1 - 20 . (canceled) 
   
   
       21 . An instruction generator that utilizes two or more parameters comprising one or more prediction mode parameters and one or more motion vector parameters to generate one or more motion compensation instructions for a prediction block in a macroblock. 
   
   
       22 . The instruction generator as recited in  claim 21 , wherein the macroblock comprises a Y component, a Cr component and a Cb component. 
   
   
       23 . The instruction generator as recited in  claim 21 , wherein each motion compensation instruction comprises an instruction descriptor followed by one or more data descriptors. 
   
   
       24 . The instruction generator as recited in  claim 23 , wherein:
 the instruction descriptor comprises at least a first data field and a second data field, the first data field indicating an operation to be performed and the second data field indicating how many of the data descriptors follow the instruction descriptor; and   each data descriptor comprises a third data field and a fourth data field, the third data field indicating a memory address of a first word in the data descriptor and the fourth data field indicating a number of words in the data description.   
   
   
       25 . The instruction generator as recited in  claim 23 , wherein each instruction descriptor is 34 bits long and each data descriptor is 34 bits long. 
   
   
       26 . The instruction generator as recited in  claim 23 , wherein each instruction descriptor contains an interlace data command. 
   
   
       27 . The instruction generator as recited in  claim 23 , wherein each instruction descriptor contains a byte offset. 
   
   
       28 . The instruction generator as recited in  claim 23 , wherein each instruction descriptor contains one or more half pixel prediction commands. 
   
   
       29 . The instruction generator as recited in  claim 23 , wherein the instruction descriptor comprises:
 a function code;   a stripe count;   a vertical half pixel prediction;   a horizontal half pixel prediction;   a byte offset; and   an interlace code.   
   
   
       30 . The instruction generator as recited in  claim 23 , wherein each data descriptor comprises:
 a starting memory address; and   a word count.   
   
   
       31 . An instruction generator comprising:
 a software and/or hardware configuration that utilizes two or more parameters to generate an instruction descriptor followed by one or more data descriptors for a prediction block in a macroblock;   the two or more parameters comprising one or more prediction mode parameters and one or more motion vector parameters;   the macroblock comprising a Y component, a Cr component and a Cb component;   the instruction descriptor comprises at least a first data field and a second data field, the first data field indicating an operation to be performed and the second data field indicating how many of the data descriptors follow the instruction descriptor; and   each data descriptor comprises a third data field and a fourth data field, the third data field indicating a memory address of a first word in the data descriptor and the fourth data field indicating a number of words in the data descriptor.   
   
   
       32 . The instruction generator as recited in  claim 31 , wherein the instruction descriptor further comprises:
 a vertical half pixel prediction;   a horizontal half pixel prediction;   a byte offset; and   an interlace code.   
   
   
       33 . A method of generating motion compensation instructions for a macroblock, wherein each macroblock comprises one or more components and each component comprises one or more prediction blocks, comprising the steps of:
 (a) generating one or more motion compensation instructions using two or more parameters including one or more prediction mode parameters and one or more motion vector parameters;   (b) repeating step (a) for each prediction block; and   (c) repeating steps (a) and (b) for each component.   
   
   
       34 . The method of generating motion compensation instructions for a macroblock as recited in  claim 33 , wherein the two or more parameters are programmable. 
   
   
       35 . The method of generating motion compensation instructions for a macroblock as recited in  claim 33 , wherein each motion compensation instruction comprises an instruction descriptor followed by one or more data descriptors. 
   
   
       36 . The method of generating motion compensation instructions for a macroblock as recited in  claim 35 , wherein:
 the instruction descriptor comprises at least a first data field and a second data field, the first data field indicating an operation to be performed and the second data field indicating how many of the data descriptors follow the instruction descriptor; and   each data descriptor comprises a third data field and a fourth data field, the third data field indicating a memory address of a first word in the data descriptor and the fourth data field indicating a number of words in the data descriptor.   
   
   
       37 . The method of generating motion compensation instructions for a macroblock as recited in  claim 33 , wherein the step of generating one or more motion compensation instructions using two or more parameters including one or more prediction mode parameters and one or more motion vector parameters comprises the steps of:
 (1) if the prediction block is a first prediction block for the component, utilizing two or more parameters including one or more prediction mode parameters and one or more motion vector parameters to generate a load instruction for the prediction block;   (2) if the prediction block is a last prediction block for the component, utilizing two or more parameters including one or more prediction mode parameters and one or more motion vector parameters to generate a merge instruction for the prediction block and a write instruction for the prediction block; and   (3) if the prediction block is not the first prediction block or the last prediction block for the component, utilizing two or more parameters including one or more prediction mode parameters and one or more motion vector parameters to generate a merge instruction for the prediction block.   
   
   
       38 . A method of generating motion compensation instructions for a macroblock comprising the steps of
 (a) generating a load instruction for a first Y prediction block in the macroblock;   (b) generating a merge instruction for a next Y prediction block in the macroblock, if necessary;   (c) repeating step (b) until the last Y prediction block is reached, if necessary;   (d) generating a write instruction for the Y prediction blocks;   (e) repeating steps (a), (b), (c) and (d) for each Cb prediction block; and   (f) repeating steps (a), (b), (c) and (d) for each Cr prediction block.   
   
   
       39 . The method of generating motion compensation instructions for a macroblock as recited in  claim 38 , wherein each motion compensation instruction comprises an instruction descriptor followed by one or more data descriptors. 
   
   
       40 . The method of generating motion compensation instructions for a macroblock as recited in  claim 39 , wherein:
 the instruction descriptor comprises at least a first data field and a second data field, the first data field indicating an operation to be performed and the second data field indicating how many of the data descriptors follow the instruction descriptor; and   each data descriptor comprises a third data field and a fourth data field, the third data field indicating a memory address of a first word in the data descriptor and the fourth data field indicating a number of words in the data descriptor.   
   
   
       41 . A digital video system comprising:
 a DVD drive;   a track buffer communicably coupled to the DVD drive;   a demultiplexer communicably coupled to the track buffer   a video input buffer communicably coupled to the demultiplexer;   a digital video decoder communicably coupled to the video input buffer, the digital video decoder utilizing at least an encoded video data stream to produce one or more output streams, the one or more output streams comprising at least a set of motion compensation instructions and a set of error terms;   each motion compensation instruction including at least an instruction descriptor followed by one or more data descriptors;   a mixer communicably coupled to the digital video decoder; and   a video renderer communicably coupled to the mixer.   
   
   
       42 . A digital video system as recited in  claim 41 , wherein:
 the instruction descriptor comprises at least a first data field and a second data field, the first data field indicating an operation to be performed and the second data field indicating how many of the data descriptors follow the instruction descriptor; and   each data descriptor comprises a third data field and a fourth data field, the third data field indicating a memory address of a first word in the data descriptor and the fourth data field indicating a number of words in the data description.   
   
   
       43 . The digital video system as recited in  claim 41 , wherein each instruction descriptor contains an interlace data command. 
   
   
       44 . The digital video system as recited in  claim 41 , wherein each instruction descriptor contains a byte offset. 
   
   
       45 . The digital video system as recited in  claim 41 , wherein each instruction descriptor contains one or more half pixel prediction commands. 
   
   
       46 . The digital video system as recited in  claim 41 , wherein the instruction descriptor comprises:
 a function code;   a stripe count;   a vertical half pixel prediction;   a horizontal half pixel prediction;   a byte offset; and   an interlace code.   
   
   
       47 . The digital video system as recited in  claim 41 , wherein each data descriptor comprises:
 a starting memory address; and   a word count.