Semiconductor integrated circuit device and method of manufacturing the same

Abstract

A semiconductor integrated circuit device includes a die pad and a semiconductor chip mounted over the die pad, having a main surface with surface electrodes and a back surface. Suspension leads support the die pad, and leads are arranged around the semiconductor chip, each of the leads having inner and outer lead portions. A first plating layer is formed at a part of the inner lead portions and a second plating layer is formed over the outer lead portion. Wires electrically connect the surface electrodes with the inner lead portions through the first plating layer. A resin body seals the die pad, the chip, the wires and the inner lead portions. The second plating layer is comprised of different materials than the first plating layer, and is a Pb-free metal layer.

1 . A semiconductor integrated circuit device comprising:
 a die pad;   a semiconductor chip mounted over said die pad, said semiconductor chip having a main surface, a back surface opposing to said main surface, and a plurality of surface electrodes formed over the main surface;   a plurality of suspension leads supporting said die pad;   a plurality of leads arranged around said semiconductor chip, each of said plurality of leads having an inner lead portion and an outer lead portion;   a first plating layer formed at a part of said inner lead portions;   a plurality of wires electrically connecting said plurality of surface electrodes of said semiconductor chip with said plurality of inner lead portion of each of said plurality of leads through said first plating layer;   a resin body sealing said die pad, said semiconductor chip, said plurality of wires and said inner lead portion of each of said plurality of leads; and   a second plating layer formed over said outer lead portions;   wherein said second plating layer is comprised of different materials than said first plating layer; and   wherein said second plating layer is a Pb-free metal layer.   
     
     
         2 . A semiconductor integrated circuit device according to  claim 1 , wherein said second plating layer has a melting point higher than Sn—Pb eutectic solder. 
     
     
         3 . A semiconductor integrated circuit device according to  claim 2 , wherein said second plating layer contains no Pd as a main composing metal. 
     
     
         4 . A semiconductor integrated circuit device according to  claim 3 , wherein said second plating layer is comprised of an alloy obtained by adding Cu and/or Bi to the Sn—Ag system metal and an alloy among Sn, In, Sb and Sn or an Sn system alloy. 
     
     
         5 . A semiconductor integrated circuit device according to  claim 1 , wherein said semiconductor chip is mounted over said die pad through an adhesive material. 
     
     
         6 . A semiconductor integrated circuit device according to  claim 5 , wherein said semiconductor chip is mounted over said die pad such that said back surface of said semiconductor chip faces to said die pad. 
     
     
         7 . A semiconductor integrated circuit device according to  claim 1 , wherein each of said plurality of leads has an upper surface, and a lower surface opposing to said upper surface; and
 wherein said first plating layer is formed at said part of said inner lead portion in said upper surface of each of said plurality of leads.   
     
     
         8 . A semiconductor integrated circuit device according to  claim 1 , wherein said first plating layer is comprised of Pd.