Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.

1 . A semiconductor device, comprising:
 a semiconductor substrate having an upper surface;   a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor being provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film provided between the floating gate electrode and the control gate electrode;   a pair of select gate transistors provided on the semiconductor substrate, the select transistors being provided with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode;   a polyplug of the first thickness provided on the semiconductor substrate situated between the second gate electrodes of the pair of select gate transistors; and   a metal plug provided on the polyplug.   
   
   
       2 . The device of  claim 1 , wherein the first gate electrode has a first width equal to a first spacing between the first gate electrodes, a second spacing between the first and the second gate electrodes, and a third spacing between the second gate electrode and the polyplug, and the second gate electrode and the polyplug each has a second width equal to a triple of the first width. 
   
   
       3 . The device of  claim 1 , wherein the polyplug has an upper-surface area greater than a bottom-surface area of the metal plug. 
   
   
       4 . The device of  claim 1 , wherein centers of the lower-layer gate electrodes of the pair of second gate electrodes are spaced apart by a fourth spacing greater than a fifth spacing between centers of the floating gates of the neighboring first gate electrodes. 
   
   
       5 . The device of  claim 1 , further comprising a gate insulating film formed on the upper surface of the semiconductor substrate situated between the pair of second gate electrodes, the gate insulating film being placed in contact with lower side-ends of the polyplug. 
   
   
       6 . A method of manufacturing a semiconductor device, comprising:
 forming a gate insulating film on a semiconductor substrate;   simultaneously forming a plurality of first conductive layers for a plurality of first gate electrodes and a plurality of second conductive layers for a plurality of second gate electrodes on the gate insulating film, the first conductive layers being formed periodically at a first spacing and the second conductive layer being formed in alignment with the first gate electrode at periodic spacing of a second spacing greater than the first spacing and further simultaneously forming a third conductive layer for a contact plug that structurally contact the semiconductor substrate situated between the plurality of second conductive layers spaced apart by the second spacing.   
   
   
       7 . The method of  claim 6 , wherein the first to third conductive layers comprise a polycrystalline silicon. 
   
   
       8 . The method of  claim 6 , wherein the first gate electrode includes a floating gate electrode and the second gate electrode includes a select gate electrode. 
   
   
       9 . The method of  claim 6 , wherein simultaneously forming the first to third conductive layers defines a third spacing between opposing sidewalls of the plurality of first conductive layers to equal a first width between the sidewalls of a single first conductive layer. 
   
   
       10 . The method of  claim 6 , wherein simultaneously forming the first to third conductive layers forms the gate insulating film at lower side-ends of the third conductive layer. 
   
   
       11 . A method of forming a semiconductor device, comprising:
 forming a gate insulating film on a memory cell transistor forming region, a select gate transistor forming region neighboring the memory cell transistor forming region, and a contact region neighboring the select transistor region respectively defined on a semiconductor substrate;   removing the gate insulating film on the contact region;   forming a first polycrystalline silicon layer having a first thickness on the contact region, the gate insulating film of the memory cell transistor forming region and the select gate transistor forming region;   forming a second polycrystalline silicon layer having a second thickness via an inter-gate insulating film on the first polycrystalline silicon layer formed on the memory cell transistor forming region, the select gate transistor forming region and the contact region;   removing the first and the second polycrystalline silicon layers and the inter-gate insulating film situated at boundaries between the memory cell transistor forming region and the select gate transistor forming region, and between the select gate transistor forming region and the contact region;   removing the second polycrystalline silicon layer and the inter-gate insulating film over the contact region to expose an upper surface of the first polycrystalline silicon layer; and   forming a metal plug on the exposed upper surface of the first polycrystalline silicon layer.