Method of manufacturing split gate type nonvolatile memory device

Abstract

A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.

1 . A method of fabricating a split gate transistor comprising:
 forming a conductive layer over a pair of floating gates separated across a source region, wherein the conductive layer is formed on portions of a tunneling insulating film extending partially over each one of the pair of floating gates and over one end of each one of the pair of floating gates opposite the source region; and   without use of a mask formed on the conductive layer, respectively forming spacer type control gates on the portions of the tunneling insulating film using a dry etching process.   
   
   
       2 . The method of  claim 1 , wherein the split gate transistor is part of a nonvolatile memory device. 
   
   
       3 . The method of  claim 1 , wherein the dry etching process is a reactive ion etching (RIE) process. 
   
   
       4 . The method of  claim 1 , wherein the conductive layer comprises a polysilicon material. 
   
   
       5 . The method of  claim 4 , further comprising:
 following formation of the spacer type control gates, converting the polysilicon material into a metal silicide.   
   
   
       6 . The method of  claim 5 , wherein the metal silicide is tungsten silicide, cobalt silicide, nickel silicide, or titanium silicide. 
   
   
       7 . The method of  claim 5 , wherein converting the polysilicon material to the metal silicide comprises; performing a rapid thermal annealing reaction between the polysilicon material and a metal layer. 
   
   
       8 . The method of  claim 1 , wherein forming the conductive layer comprises; directly depositing a tungsten silicide layer using a chemical vapor deposition (CVD) process. 
   
   
       9 . A method of fabricating a split gate transistor comprising:
 forming first and second portions of a tunnel insulating film on opposing sidewalls of an insulating film plug separating a pair of floating gates across a source region, such that each one of the first and second portions of the tunnel insulating film extends partially over a respective one of the pair of floating gates and covers one end of the respective one of the pair of floating gates opposite the source region;   forming a polysilicon layer on the first and second portions of the tunneling insulating film; and   without the use of a mask formed on the polysilicon layer, respectively forming first and second spacer type control gates on the first and second portions of the tunneling insulating film using a reactive ion etching (RIE) process.   
   
   
       10 . The method of  claim 9 , further comprising:
 following formation of the first and second spacer type control gates, converting the polysilicon material into a metal silicide.