Flash Memory and Methods of Fabricating Flash Memory

Abstract

Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.

1 . A method of fabricating a flash memory comprising:
 depositing a tunneling oxide on a silicon substrate;   depositing a first polysilicon layer to form a first floating gate on the tunneling oxide;   depositing a first mask layer on the first polysilicon substrate;   etching the first mask layer, the first polysilicon substrate, the tunneling oxide and the silicon substrate using a predetermined pattern to form STI and the first floating gate;   depositing field oxide in the STI;   depositing a second polysilicon layer to form a second floating gate over the first mask layer and the field oxide;   depositing a second mask layer over the second polysilicon layer;   etching the second mask layer to form spacers on side-wall portions of the second polysilicon layer, wherein the spacers are in contact with the side-wall portions and an upper surface of the second polysilicon layer below the spacers;   removing a portion of the second polysilicon layer using the spacers as a mask to form a second floating gate;   removing the spacers and the first mask layer; and   depositing a dielectric layer and a third polysilicon layer to form a control gate over the first floating gate and the second floating gate.   
   
   
       2 . A method as defined by  claim 1 , wherein depositing the field oxide in the STI comprises depositing a field oxide layer and removing a portion of the field oxide by an etching process until approximately half of a sidewall of the first floating gate is exposed. 
   
   
       3 . A method as defined by  claim 1 , wherein the first mask layer is a nitride layer. 
   
   
       4 . A method as defined by  claim 1 , wherein the second mask layer is an oxide layer. 
   
   
       5 . A method as defined by  claim 1 , wherein the portion of the second polysilicon layer is removed by a reactive ion etching process. 
   
   
       6 . A method as defined by  claim 1 , wherein the first floating gate is connected with the second floating gate to form a floating gate. 
   
   
       7 . A method as defined by  claim 1 , wherein the second floating gate is a step-shaped floating gate. 
   
   
       8 . A method as defined by  claim 7 , wherein the step-shaped second floating gate includes a first part extending upward above the first floating gate and a second part extending sideward from the first part. 
   
   
       9 . A method as defined by  claim 8 , wherein the second part of the second floating gate is in contact with the STI. 
   
   
       10 . A method as defined by  claim 1 , wherein the second floating gate does not extend over the first floating gate. 
   
   
       11 . A method as defined by  claim 1 , wherein the second floating gate is located above the STI adjacent the first floating gate.