Semiconductor device, method of manufacture thereof and semiconductor integrated circuit

Abstract

An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

1 . A method of manufacturing a semiconductor device, comprising the steps of:
 (a) preparing a semiconductor substrate including an insulating layer and a semiconductor layer provided on said insulating layer;   (b) forming a silicon nitride film above said semiconductor layer;   (c) patterning said silicon nitride film by a photolithography technique;   (d) etching said semiconductor layer to a depth that does not reach said insulating layer, with said silicon nitride film having been patterned as a mask;   (e) forming a photoresist above said silicon nitride film having been patterned and said semiconductor layer having been etched, to pattern said photoresist;   (f) further etching part of said semiconductor layer having been etched to a depth that reaches said insulating layer, with said photoresist and said silicon nitride film having been patterned as a mask; and   (g) burying an insulating film both in a portion of said semiconductor layer having been etched to a depth that does not reach said insulating layer and in a portion of said semiconductor layer having been etched to a depth that reaches said insulating layer, to form an element isolation insulating film.   
   
   
       2 . The method of manufacturing a semiconductor device according to  claim 1 , wherein
 said element isolation insulating film reaching said insulating layer is an element isolation insulating film between different MIS transistors that extends in a first direction, said first direction being perpendicular both to a thickness direction of said semiconductor layer and to a second direction in which gate electrodes of said MIS transistors extend, and   said element isolation insulating film not reaching said insulating layer is an element isolation insulating film provided near body regions of said MIS transistors.