Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage

Abstract

In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

1 - 9 . (canceled) 
   
   
       10 . A non-volatile semiconductor memory device comprising:
 a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing information by variation in threshold voltage;   a plurality of word lines associated with said plurality of rows, respectively;   a plurality of bit lines associated with said plurality of columns, respectively;   a plurality of sense latches associated with said plurality of bit lines, respectively; and   a write circuit writing information to each of said plurality of memory cells, wherein said write circuit is configured for:
 causing each sense latch associated with a memory cell of a plurality of memory cells associated with one selected word line that is subjected to a write to latch a first signal, and causing each sense latch associated with a memory cell that is not subjected to said write to latch a second signal; 
 performing said write to and verifying each of said plurality of memory cells associated with said selected word line that is associated with said sense latch latching said first signal, and causing each sense latch associated with said memory cell in which said write is completed to latch said second signal; and 
 re-verifying said memory cell subjected to said write, and causing each sense latch associated with said memory cell in which said write is detected to be insufficiently done to latch said first signal, wherein in said re-verifying, each bit line associated with said memory cell that is not subjected to said write is previously discharged. 
   
   
   
       11 . The non-volatile semiconductor memory device according to  claim 10 , wherein:
 the write circuit repeatedly perform said write to and verifying said plurality of memory cells associated with said selected word line until said plurality of sense latches all latch said second signal; and   said write circuit is further configured for performing a write to each memory cell associated with said sense latch latching said first signal after said re-verifying.   
   
   
       12 . The non-volatile semiconductor memory device according to  claim 10 , wherein if there is any sense latch latching said first signal in said re-verifying, said write circuit again performs said write and said verifying. 
   
   
       13 . The non-volatile semiconductor memory device according to  claim 10 , wherein said re-verifying and detecting a memory cell in which said write is insufficiently done is performed in such a way that each bit line associated with said memory cell subjected to said write is precharged and each bit line associated with said memory cell that is not subjected to said write is discharged, and a re-verification voltage is applied to said selected word line and each bit line associated with a memory cell having a threshold voltage of at most said re-verification voltage is discharged and thereafter each bit line associated with said memory cell that is not subjected to said write is precharged. 
   
   
       14 . The non-volatile semiconductor memory device according to  claim 10 , wherein in said re-verifying, each bit line associated with said memory cell subjected to said write is precharged and each bit line associated with said memory cell that is not subjected to said write is also discharged by precharging all of said plurality of bit lines and thereafter applying a voltage to said selected word line to make a decision, said voltage being lower than a voltage applied in said verifying. 
   
   
       15 . A non-volatile semiconductor memory device comprising:
 a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing information by variation in threshold voltage;   a plurality of word lines associated with said plurality of rows, respectively;   a plurality of bit lines associated with said plurality of columns, respectively;   a plurality of sense latches associated with said plurality of bit lines, respectively; and   a write circuit writing information to each of said plurality of memory cells, wherein said write circuit is configured for:
 causing each sense latch associated with a memory cell of a plurality of memory cells associated with one selected word line that is subjected to a write to latch a first signal, and causing each sense latch associated with a memory cell that is not subjected to said write to latch a second signal; 
 performing said write to and verifying with a verification voltage each of said plurality of memory cells associated with said selected word line that is associated with said sense latch latching said first signal, and causing each sense latch associated with said memory cell said write to which is completed to latch said second signal; 
 causing said plurality of sense latches to all latch said first signal after said write and said verifying are repeated to cause said plurality of sense latches to all latch said second signal; and 
 performing a write, in a writing condition different from that in said write performed in said write and said verifying, to each memory cell associated with said sense latch latching said first signal. 
   
   
   
       16 . The non-volatile semiconductor memory device according to  claim 15 , wherein said write in said writing condition different from that in said write performed in said write and said verifying is performed under such a condition that an amount of electric charge introduced into said memory cell is smaller than in said second step. 
   
   
       17 . A non-volatile semiconductor memory device comprising:
 a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing information by variation in threshold voltage;   a plurality of word lines associated with said plurality of rows, respectively;   a plurality of bit lines associated with said plurality of columns, respectively;   a plurality of sense latches associated with said plurality of bit lines, respectively; and   a write circuit writing information to each of said plurality of memory cells, wherein said write circuit is configured for:
 causing each sense latch associated with a memory cell of a plurality of memory cells associated with one selected word line that is subjected to a write to latch a first signal, and causing each sense latch associated with a memory cell that is not subjected to said write to latch a second signal; 
 performing said write to and verifying with a verification voltage each of said plurality of memory cells associated with said selected word line that is associated with said sense latch latching said first signal, and causing each sense latch associated with said memory cell in which said write is completed to latch said second signal; 
 causing each sense latch associated with said memory cell subjected to said write to latch said first signal after said second step is repeated to cause said plurality of sense latches to all latch said second signal; and 
 performing a write, in a writing condition different from that in said write performed in said write and said verifying, to each memory cell associated with said sense latch latching said first signal. 
   
   
   
       18 . The non-volatile semiconductor memory device according to  claim 17 , wherein said write in the writing condition different from that in said writing performed in said writing and said verifying is performed under such a condition that an amount of electric charge introduced into said memory cell is smaller than in said second step.