Nand flash cell structure

Abstract

NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel r ds resistance and decreased “narrow width” effect, allowing for increased scaling of NAND memory cell strings. In addition, the required voltages for reading and programming operations are reduced, allowing the use of more efficient, lower voltage charge pumps and a reduction circuit element feature sizes and layouts. Cell inhibit of unselected cells is also increased, reducing the likelihood of cell disturb in the memory array. Operation speed is improved by increasing read current of the selected NAND string and by increasing the ability to overcome the RC time constants of circuit lines and capacitances through lowered voltage swings and increased current supplies.

1 . A NAND configuration string of floating gate memory cells, comprising:
 a plurality of depletion mode floating gate memory cells coupled as a single string of memory cells, wherein the single string of memory cells is formed above a single continuous channel region.   
   
   
       2 . The string of floating gate memory cells of  claim 1 , further comprising a bitline coupled to a first end of the single string of memory cells through a depletion mode select transistor. 
   
   
       3 . The string of floating gate memory cells of  claim 1 , further comprising a bitline coupled to a first end of the single string of memory cells through a enhancement mode select transistor. 
   
   
       4 . The string of floating gate memory cells of  claim 1 , further comprising a source line coupled to a first end of the single string of memory cells through a depletion mode select transistor. 
   
   
       5 . The string of floating gate memory cells of  claim 1 , further comprising a source line coupled to a first end of the single string of memory cells through an enhancement mode select transistor. 
   
   
       6 . The string of floating gate memory cells of  claim 1 , wherein the single continuous channel region is a depletion channel region. 
   
   
       7 . The string of floating gate memory cells of  claim 6 , wherein the single continuous channel region is a resistive diffusion region. 
   
   
       8 . The string of floating gate memory cells of  claim 1 , further comprising a doped well formed at a first end of the continuous channel region and a second doped well formed at a second end of the continuous channel region. 
   
   
       9 . The string of floating gate memory cells of  claim 1 , wherein the plurality of depletion mode floating gate memory cells are one of depletion mode P-FET and depletion mode N-FET floating gate memory cells. 
   
   
       10 . The string of floating gate memory cells of  claim 1 , wherein the plurality of depletion mode floating gate memory cells have a negative native UV erased threshold voltage (UV-Vth). 
   
   
       11 . The string of floating gate memory cells of  claim 1 , further comprising a plurality of word lines, each word line coupled to a memory cell of the plurality of depletion mode floating gate memory cells. 
   
   
       12 . A NAND configuration string of floating gate memory cells, comprising:
 a single continuous channel region formed in a substrate; and   a plurality of depletion mode memory cells formed in a string above the single continuous channel region, each depletion mode memory cell comprising:
 a tunnel region formed above the single continuous channel region; 
 a floating gate region formed above the tunnel region; 
 a gate insulator region formed above the floating gate region; and 
 a control gate formed above the gate insulator region. 
   
   
   
       13 . The NAND configuration string of  claim 12 , further comprising:
 a first select gate coupled to a first end of the single continuous channel region; and   a second select gate coupled to a second end of the single continuous channel region.   
   
   
       14 . The NAND configuration string of  claim 13 , wherein the first select gate and/or the second select gate are depletion mode FET transistors. 
   
   
       15 . The NAND configuration string of  claim 13 , further comprising:
 a bitline coupled to the first select gate; and   a source line coupled to the second select gate.   
   
   
       16 . A NAND configuration string of floating gate memory cells, comprising:
 a single continuous channel region formed in a substrate, wherein a first doped well is formed in the substrate at a first end of the single continuous channel region and a second doped well is formed in the substrate at a second end of the single continuous channel region; and
 a plurality of depletion mode memory cells formed in a string above the single continuous channel region and between the first and the second doped wells. 
   
   
   
       17 . The string of floating gate memory cells of  claim 16 , wherein each depletion mode memory cell comprises:
 a tunnel region formed above the single continuous channel region;   a floating gate region formed above the tunnel region;   a gate insulator region formed above the floating gate region; and   a control gate formed above the gate insulator region.   
   
   
       18 . The string of floating gate memory cells of  claim 17 , further comprising a plurality of word lines, each word line coupled to a control gate of each memory cell of the string of floating gate memory cells. 
   
   
       19 . The string of floating gate memory cells of  claim 16 , wherein the single continuous channel region comprises a single resistive continuous channel region. 
   
   
       20 . The string of floating gate memory cells of  claim 16 , further comprising:
 a bitline coupled by a first select gate to a first end of the string of floating gate memory cells; and   a source line coupled by a second select gate to a second end of the string of floating gate memory cells.   
   
   
       21 . The string of floating gate memory cells of  claim 20 , wherein the first and/or the second select gate is a depletion mode transistor. 
   
   
       22 . The string of floating gate memory cells of  claim 16 , wherein the doped wells are one of n+ and p− type doped regions. 
   
   
       23 . The string of floating gate memory cells of  claim 20 , wherein the first doped well is a source region of the first select gate and the second doped well is a drain region for the second select gate. 
   
   
       24 . A memory device, comprising:
 a control circuit; and   an array of non-volatile memory cells arranged in a plurality of strings of memory cells wherein each string of memory cells comprises a plurality of depletion mode floating gate memory cells coupled as a single string of memory cells, where each single string of memory cells is formed above a single continuous channel region.   
   
   
       25 . The memory device of  claim 24 , wherein each string of memory cells are formed in a substrate tub, where the substrate tub is formed in a substrate. 
   
   
       26 . The memory device of  claim 25 , wherein the control circuit is adapted to bias each substrate tub to a selected precharge voltage level during a program operation performed on a string of memory cells. 
   
   
       27 . The memory device of  claim 26 , wherein the selected precharge voltage level is Vcc. 
   
   
       28 . The memory device of  claim 24 , further comprising a plurality of bitlines coupled to a single end of one or more strings of memory cells each by a select transistor, wherein the select transistor is one of depletion mode and enhancement mode transistors. 
   
   
       29 . The memory device of  claim 24 , further comprising a plurality of source lines coupled to a single end of one or more strings of memory cells each by a select transistor, wherein the select transistor is one of depletion mode and enhancement mode transistors.