Low resistance plate line bus architecture

Abstract

An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

1 . An array of FeRAM memory cells, comprising:
 a plurality of columns arranged along a bit line direction and a plurality of rows arranged along a word line direction;   a plurality of plate lines arranged along a word line direction;   a common plate line driver connected to, and configured to drive the plurality of plate lines; and   wherein the plate line interconnection is made outside the memory array on the opposite side of the array from the common plate line driver.   
   
   
       2 . The array of  claim 1 , wherein a cell in the array of FeRAM memory cells comprises a 1T1C cell. 
   
   
       3 . The array of  claim 1 , wherein a cell in the array of FeRAM memory cells comprises a 2T2C cell. 
   
   
       4 . The array of  claim 1 , wherein a cell in the array of FeRAM memory cells comprises a pair of 1T1C cells. 
   
   
       5 . The array of  claim 4 , wherein the 1T C cells in the pair belong to different 2T2C cells. 
   
   
       6 . The array of  claim 1 , wherein a cell in the array of FeRAM memory cells comprises a pass gate transistor and one capacitor. 
   
   
       7 . The array of  claim 1 , wherein a cell in the array of FeRAM memory cells comprises two pass gate transistors and two capacitors. 
   
   
       8 . The array of  claim 1 , wherein a cell in the array of FeRAM memory cells comprises a first pass gate transistor and a first capacitor and a second pass gate transistor a second capacitor. 
   
   
       9 . The array of  claim 8 , wherein the first pass gate transistor and the first capacitor belong to a first 1T1C cell, and the second pass gate transistor and the second capacitor belong to a second 1T1C cell.