Method of manufacturing non-volatile memory

Abstract

A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively.

1 . A method of manufacturing the non-volatile memory, comprising:
 providing a substrate;   forming a patterned mask layer on the substrate;   forming a tunnel dielectric layer and a first conductive layer on the substrate;   removing the first conductive layer on the top of the mask layer to form a plurality of second conductive layers on the sidewall of the mask layer and the substrate;   removing the mask layer;   forming a source region in the substrate between the second conductive layers;   forming an inter-gate dielectric layer on the substrate;   forming a third conductive layer on the inter-gate dielectric layer;   patterning the third conductive layer, the inter-gate dielectric layer, and the second conductive layers;   forming a dielectric layer on the substrate and on the exposed sidewalls of the third conductive layer and the second conductive layers;   forming a fourth conductive layer on the sidewall of the third conductive layer; and   forming a drain region in the substrate outside the fourth conductive layer.   
   
   
       2 . The method of manufacturing the non-volatile memory as claimed in  claim 1 , wherein the cross-section of each of the patterned second conductive layers present an L-shape, and the patterned second conductive layer comprises a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate, and the central region is adjacent to the source region. 
   
   
       3 . The method of manufacturing the non-volatile memory as claimed in  claim 2 , wherein the material of the second conductive layers comprises doped polysilicon. 
   
   
       4 . The method of manufacturing the non-volatile memory as claimed in  claim 3 , wherein a process of forming the dielectric layer on the sidewall of the lateral region of the second conductive layer comprises thermal oxidation process. 
   
   
       5 . The method of manufacturing the non-volatile memory as claimed in  claim 4 , wherein after the thermal oxidation process, the sidewall of the lateral region takes the shape of a circular arc curve. 
   
   
       6 . The method of manufacturing the non-volatile memory as claimed in  claim 1 , wherein the step of patterning the third conductive layer comprises:
 forming a patterned photoresist layer on the third conductive layer;   removing a portion of the third conductive layer by using the patterned photoresist layer as a mask; and   removing the patterned photoresist layer.   
   
   
       7 . The method of manufacturing the non-volatile memory as claimed in  claim 1 , wherein the step of patterning the third conductive layer further comprises removing a portion of the third conductive layer by using the inter-gate dielectric layer as a stop layer. 
   
   
       8 . The method of manufacturing the non-volatile memory as claimed in  claim 1 , wherein the method of patterning the second conductive layers further comprises using the patterned third conductive layer as a self-aligned mask. 
   
   
       9 . The method of manufacturing the non-volatile memory as claimed in  claim 1 , wherein the step of patterning the inter-gate dielectric layer and the second conductive layers further comprises patterning the tunnel dielectric layer. 
   
   
       10 . The method of manufacturing the non-volatile memory as claimed in  claim 1 , wherein the method of forming the tunnel dielectric layer comprises thermal oxidation. 
   
   
       11 . A method of manufacturing the non-volatile memory, comprising:
 providing a substrate, wherein a plurality of isolation structures is formed on the substrate in arrays and a mask layer is filled in the intervals between the isolation structures;   removing a portion of the mask layer and leaving the mask layer between two adjacent rows of the isolation structures;   forming a tunnel dielectric layer and a first conductive layer on the substrate;   removing the first conductive layer on the top of the mask layer and the top of the isolation structures to form a plurality of second conductive layers on two sidewalls of the mask layer and between the isolation structures;   removing portions of the isolation structures;   removing the mask layer;   forming a source region in the substrate between the second conductive layers;   forming an inter-gate dielectric layer on the substrate;   forming a third conductive layer on the inter-gate dielectric layer;   patterning the third conductive layer to cover the source region and portions of the second conductive layers on the both sides of the source region;   removing portions of the inter-gate dielectric layer and the second conductive layers by using the third conductive layer as the self-aligned mask;   forming a dielectric layer on the substrate and the exposed sidewalls of the third conductive layer and second conductive layers;   forming a fourth conductive layer on the sidewall of the third conductive layer; and   forming a drain region in the substrate outside the fourth conductive layer.   
   
   
       12 . The method of manufacturing the non-volatile memory as claimed in  claim 11 , wherein the cross-section of each of the patterned second conductive layers presents an L-shape, and the patterned second conductive layer comprises a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate, and the central region is adjacent to the source region. 
   
   
       13 . The method of manufacturing the non-volatile memory as claimed in  claim 12 , wherein the method of forming the dielectric layer on the sidewall of the lateral region of the second conductive layers comprises thermal oxidation process. 
   
   
       14 . The method of manufacturing the non-volatile memory as claimed in  claim 13 , wherein after the thermal oxidation process, the sidewall of the lateral region takes the shape of a circular arc curve. 
   
   
       15 . The method of manufacturing the non-volatile memory as claimed in  claim 11 , wherein after the step of removing portion of the isolation structures, the top of the isolation structures is at least lower than that of the second conductive layers. 
   
   
       16 . The method of manufacturing the non-volatile memory as claimed in  claim 11 , wherein the step of patterning the third conductive layer further comprises removing a portion of the third conductive layer by using the inter-gate dielectric layer as a stop layer. 
   
   
       17 . The method of manufacturing the non-volatile memory as claimed in  claim 11 , wherein the step of removing a portion of the inter-gate dielectric layer and the second conductive layers further comprises removing a portion of the tunnel dielectric layer. 
   
   
       18 . The method of manufacturing the non-volatile memory as claimed in  claim 11 , wherein the method of forming the tunnel dielectric layer comprises thermal oxidation.