Method of forming contact plugs

Abstract

A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

1 . A method of forming cell bitline contact plugs, comprising:
 providing a semiconductor substrate with MOS transistors, wherein the semiconductor substrate has a cell area with an array of memory cells and a periphery area with peripheral circuits;   forming at least a cell bitline contact at the cell area;   forming bitline pattern openings at the periphery area;   forming polysilicon spacers on sidewalls of the bitline pattern openings and partially filling polysilicon in the cell bitline contact at the same time, wherein the polysilicon spacers are formed by first depositing a doped polysilicon layer and then etching back the doped silicon layer;   forming a substrate contact and a gate contact within the openings;   forming a trench around each of the substrate contact and the gate contact by using the polysilicon spacers and the bitline pattern openings as an etching mask; and   filling a metal layer into the cell bitline contact, the substrate contact and the gate contact to form a cell bitline contact plug, a substrate contact plug and a gate contact plug.   
   
   
       2 . The method of  claim 1 , further comprising a step of forming a barrier layer in the bitline contact, the substrate contact, and the gate contact between the step of forming the trenches and the step of filling the metal. 
   
   
       3 . The method of  claim 1 , further comprising a step of planarizing the metal layer after the step of filling the metal. 
   
   
       4 . A method of forming contact plugs, comprising:
 providing a semiconductor substrate with MOS transistors;   forming a dielectric layer on the MOS transistors and the semiconductor substrate;   forming a mask layer on the dielectric layer;   forming pattern openings in the mask layer to expose the dielectric layer;   forming polysilicon spacers on sidewalls of the pattern openings, wherein the polysilicon spacers are formed by first depositing a doped polysilicon layer and then etching back the doped silicon layer;   forming and patterning a photoresist layer on the top of the polysilicon spacers, the mask layer and the dielectric layer;   forming a substrate contact and a gate contact within the pattern openings by using the photoresist layer as a first etching mask, wherein the substrate contact is in direct contact with the semiconductor substrate;   forming a trench around each of the substrate contact and the gate contact by using a second etching mask consisting of the polysilicon spacers and the mask layer; and   filling a metal layer into the substrate contact, the gate contact and the trench around each of the substrate contact and the gate contact to form a substrate contact plug and a gate contact plug.   
   
   
       5 . The method of  claim 4 , wherein the semiconductor substrate has a cell area with an array of memory cells and a periphery area with peripheral circuits, and the pattern openings are formed in the mask layer at the periphery area. 
   
   
       6 . The method of  claim 4 , further comprising a step of forming a barrier layer in the substrate contact, and the gate contact between the step of forming the trenches and the step of filling the metal. 
   
   
       7 . The method of  claim 4 , further comprising a step of planarizing the metal layer after the step of filling the metal. 
   
   
       8 . The method of  claim 4 , wherein the mask layer is a polysilicon layer. 
   
   
       9 . The method of  claim 4 , wherein the pattern openings are bitline pattern openings.