Flash Memory Device and Method of Manufacturing the Same

Abstract

Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region.

1 . A flash memory device comprising:
 a plurality of trench lines in an isolation region of a semiconductor substrate;   a common source region in a word line (WL) direction under a surface portion of the semiconductor substrate;   a plurality of gate lines perpendicular to the trench line;   a drain region on an opposite side of the gate line from the common source region;   a drain contact over a portion of the drain region; and   a uniform by-product layer on the common source region.   
   
   
       2 . The flash memory device as claimed in  claim 1 , wherein ions implanted into a surface portion of the trench region are also present in the common source region. 
   
   
       3 . The flash memory device as claimed in  claim 1 , wherein the by-product layer is configured to prevent a loss of a portion of the surface of the semiconductor substrate during ion implantation into the common source region and/or prevent a surface resistance from increasing in the common source region. 
   
   
       4 . The flash memory device as claimed in  claim 1 , wherein a common source line in the common source region has a substantially constant depth. 
   
   
       5 . The flash memory device as claimed in  claim 1 , wherein the trench lines are parallel with a bit line (BL). 
   
   
       6 . The flash memory device as claimed in  claim 1 , wherein the gate line is parallel with a word line (WL). 
   
   
       7 . The flash memory device as claimed in  claim 1 , wherein the by-product layer comprises a fluorocarbon- and/or hydrofluorocarbon-based polymer. 
   
   
       8 . The flash memory device as claimed in  claim 1 , wherein the by-product layer is on a sidewall, a bottom wall and an upper wall portion of the isolation region in the semiconductor substrate.