US2008320454A1PendingUtilityA1

Variable address length compiler and processor improved in address management

Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: May 27, 1993Filed: Dec 4, 2006Published: Dec 25, 2008
Est. expiryMay 27, 2013(expired)· nominal 20-yr term from priority
G06F 9/342G06F 9/34G06F 9/30145G06F 9/3013G06F 9/30112G06F 9/30014G06F 8/52G06F 8/47G06F 8/447G06F 8/423G06F 9/30167
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

Claims

exact text as granted — not AI-modified
1 - 61 . (canceled) 
   
   
       62 . A processor for operating certain data in accordance with an instruction in a program, comprising:
 a first register unit;   a second register unit;   a sign-extending unit;   a zero-extending unit; and   an instruction decoding unit for decoding an instruction in the program to detect a first type instruction and a second type instruction, said first type instruction including an instruction to store data into said first register unit, said second type instruction including an instruction to store data into said second register unit, with said first type instruction and said second type instruction having different destination operands to designate whether to store data into said first register unit or said second register unit;   wherein said zero-extending unit zero-extends data when a first type instruction is detected and said sign-extending unit sign-extends data when a second type instruction is detected.   
   
   
       63 . The processor of  claim 62 , wherein said data is an immediate data included in the first type instruction and the second type instruction.

Join the waitlist — get patent alerts

Track US2008320454A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.