Split gate type nonvolatile memory device and method of fabricating the same

Abstract

In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.

1 . A method of fabricating a split gate type nonvolatile memory device comprising:
 forming a supplementary layer pattern on a portion of a semiconductor substrate;   forming a gate insulating layer on the semiconductor substrate and the supplementary layer pattern;   forming a floating gate and a floating gate poly-insulating layer on a portion of the gate insulating layer, the floating gate being formed to overlap a side surface of the supplementary layer pattern and to extend onto a portion of a top surface of the supplementary layer pattern;   forming a tunneling insulating layer that covers the side surface of the floating gate; and   forming a control gate on the tunneling insulating layer and the floating gate poly-insulating layer so that the control gate overlaps the floating gate.   
   
   
       2 . The method of  claim 1 , wherein forming the floating gate and the floating gate poly-insulating layer comprises:
 depositing a polysilicon layer on the gate insulating layer;   forming a first mask exposing a predetermined portion of the polysilicon layer;   forming the floating gate poly-insulating layer by oxidizing the exposed portion of the polysilicon layer; and   forming the floating gate by etching the polysilicon layer using the floating gate poly-insulating layer as a second mask after removing the first mask.   
   
   
       3 . The method of  claim 2 , further comprising forming a source region after forming the floating gate. 
   
   
       4 . The method of  claim 3 , wherein the source region is formed by implanting impurity ions into the supplementary layer pattern and subsequently diffusing the impurity ions into the semiconductor substrate. 
   
   
       5 . The method of  claim 1 , wherein forming the floating gate and the floating gate poly-insulating layer comprises:
 depositing a polysilicon layer on the gate insulating layer;   forming an insulating layer on the polysilicon layer;   forming the floating gate poly-insulating layer by etching a predetermined portion of the insulating layer; and   forming the floating gate by etching the polysilicon layer using the floating gate poly-insulating layer as a mask.   
   
   
       6 . The method of  claim 5 , wherein the floating gate poly-insulating layer comprises a stacked silicon oxide layer and a silicon nitride layer. 
   
   
       7 . The method of  claim 6 , further comprising forming a source region after the forming of the supplementary layer pattern. 
   
   
       8 . The method of  claim 7 , wherein the source region is formed by implanting impurity ions into the supplementary layer pattern and subsequently diffusing the impurity ions into the semiconductor substrate.