Method of fabricating thin film transistor and method of fabricating liquid crystal display

Abstract

A method of fabricating a thin film transistor is provided. First, a patterned dielectric layer is formed over a substrate. A metallic layer is formed over the substrate to cover the patterned dielectric layer. Thereafter, the metallic layer is planarized until the patterned dielectric layer is exposed. The remained metallic layer serves as a gate. An insulating layer is formed over the patterned dielectric layer and the gate, and then a semiconductor layer is formed over the gate insulating layer above the gate. A source and a drain are formed over the semiconductor layer.

1 . A method of fabricating a thin film transistor comprising the steps of:
 providing a substrate;   forming a first patterned dielectric layer having at least one first opening over the substrate;   forming a first metallic layer cover the first patterned dielectric layer and the first opening;   performing a chemical-mechanical polishing operation to planarize the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate;   forming a gate insulating layer over the first patterned dielectric layer and the gate;   forming a semiconductor layer over the gate insulating layer above the gate; and   forming a source and a drain over the semiconductor layer.   
   
   
       2 . The method of  claim 1 , wherein the material constituting the first metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. 
   
   
       3 . The method of  claim 1 , wherein the step of forming the source and the drain over the semiconductor layer comprises:
 forming a second patterned dielectric layer over the gate insulating layer;   forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; and   performing a planarization process to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form the source and the drain in the second opening.   
   
   
       4 . The method of  claim 3 , wherein the planarization process includes a chemical-mechanical polishing operation. 
   
   
       5 . The method of  claim 3 , wherein the material constituting the second metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. 
   
   
       6 . The method of  claim 3 , further comprising removing the second patterned dielectric layer after forming the source and the drain. 
   
   
       7 . The method of  claim 1 , further comprising forming a stress-buffering layer over the substrate before forming the first patterned dielectric layer over the substrate. 
   
   
       8 . The method of  claim 7 , wherein the material constituting the stress-buffering layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a combination thereof. 
   
   
       9 . The method of  claim 1 , wherein the semiconductor layer comprises a channel layer and an ohmic contact layer. 
   
   
       10 . A method of fabricating a thin film transistor, comprising:
 providing a substrate;   forming a first patterned dielectric layer having at least one first opening over the substrate;   forming a first metallic layer cover the first patterned dielectric layer and the first opening;   performing a first chemical-mechanical polishing operation to planarize the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate;   forming a gate insulating layer over the substrate to cover the gate;   forming a semiconductor layer over the gate insulating layer above the gate;   forming a second patterned dielectric layer over the gate insulating layer;   forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; and   performing a second chemical-mechanical polishing operation to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form a source and a drain in the second opening.   
   
   
       11 . The method of  claim 10 , wherein the material constituting the metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. 
   
   
       12 . The method of  claim 10 , further comprising forming a stress-buffering layer over the substrate before forming the gate over the substrate. 
   
   
       13 . The method of  claim 12 , wherein the material constituting the stress-buffering layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a combination thereof. 
   
   
       14 . The method of  claim 10 , wherein the semiconductor layer comprises a channel layer and an ohmic contact layer. 
   
   
       15 . A method of fabricating a liquid crystal display, comprising the steps of:
 providing a first substrate;   forming a thin film transistor array layer over the first substrate, wherein the thin film transistor array layer comprises a plurality of thin film transistors and a plurality of pixel electrodes, each thin film transistor having a gate, a source and a drain, and the method of forming the gate comprising:   forming a first patterned dielectric layer having at least one first opening over the first substrate;   forming a first metallic layer cover the first patterned dielectric layer and the first opening;   performing a first chemical-mechanical polishing operation to planarize the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate;   providing a second substrate; and   forming a liquid crystal layer between the first substrate and the second substrate.   
   
   
       16 . The method of  claim 15 , wherein the material constituting the first metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. 
   
   
       17 . The method of  claim 15 , wherein the second substrate further comprises a color filter layer disposed thereon. 
   
   
       18 . The method of  claim 15 , wherein the method of forming the source and the drain comprises:
 forming a second patterned dielectric layer over the gate insulating layer;   forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; and   performing a planarization process to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form the source and the drain in the second opening.   
   
   
       19 . The method of  claim 18 , wherein the planarization process includes a chemical-mechanical polishing operation.