Circuit-pattern inspecting apparatus and method

Abstract

A circuit pattern inspection apparatus and inspection method facilitate the creation of a recipe and the confirmation of a defect. The apparatus and method employ a dialogue-based operation for the creation of a recipe and the confirmation of a defect. Input items (such as contrast, calibration, etc.) for the recipe creation and their purposes are clarified. Input items (such as clustering, filtering, etc.) for the defect confirmation and their purposes are also clarified. The results obtained on the basis of these inputs are registered in the recipe.

1 - 5 . (canceled) 
   
   
       6 . A circuit pattern inspection apparatus comprising:
 an irradiation means for irradiating the surface of a substrate on which a wafer circuit pattern is formed with either light, laser light, or a charged-particle beam;   a detection means for detecting a signal produced by the substrate upon irradiation;   an inspection image acquisition means for acquiring images of the wafer circuit pattern as inspection images by converting the signal detected by the detection means into images;   a defect determination means for comparing the inspection images obtained by the inspection image acquisition means with a reference image different from the inspection images that are acquired from an identical circuit pattern so as to determine a defect portion produced on the circuit pattern from which the inspection images have been acquired;   an analysis result display means for generating a defect confirmation screen on which the inspection images acquired by the inspection image acquisition means, an analysis image based on the inspection images and another analysis image based on the result of defect determination made by the defect determination means are arranged; and   an input means for entering information on a defect confirmation screen generated by the analysis result display means in a dialog mode,   wherein the defect confirmation screen includes a map display area, an image display area, a list display area, and a graph display area, and   wherein the screen size and display position of each of the map display area, the image display area, the list display area, and the graph display area can be changed.   
   
   
       7 . The circuit pattern inspection apparatus according to  claim 6 , wherein the settings for the screen size and display position of each of the map display area, the image display area, the list display area, and the graph display area are, once changed, valid upon next startup. 
   
   
       8 . The circuit pattern inspection apparatus according to  claim 6 , wherein the screen size and display position of each of the map display area, the image display area, the list display area, and the graph display area can be returned to default startup coordinates and size. 
   
   
       9 . A circuit pattern inspection apparatus comprising:
 an irradiation means for irradiating the surface of a substrate on which a wafer circuit pattern is formed with either light, laser light, or a charged-particle beam;   a detection means for detecting a signal produced by the substrate upon irradiation;   an inspection image acquisition means for acquiring images of the wafer circuit pattern as inspection images by converting the signal detected by the detection means into images;   a defect determination means for comparing the inspection images obtained by the inspection image acquisition means with a reference image different from the inspection images that are acquired from an identical circuit pattern so as to determine a defect portion produced on the circuit pattern from which the inspection images have been acquired;   an analysis result display means for generating a defect confirmation screen on which the inspection images acquired by the inspection image acquisition means, an analysis image based on the inspection image, and another analysis image based on the result of defect determination made by the defect determination means are arranged; and   an input means for entering information on a defect confirmation screen generated by the analysis result display means in a dialog mode;   wherein the defect confirmation screen includes a map display area, and   wherein the analysis result display means includes a map process processing unit, the map process processing unit performing display on the map display area with the use of one of the three following map rendering modes: a wafer overall rendering mode in which the entirety of a wafer is displayed, a die rendering mode in which one or more dies of a wafer are displayed in a superposed manner, and a shot rendering mode in which one or more shots of a wafer are displayed in a superposed manner.   
   
   
       10 . The circuit pattern inspection apparatus according to  claim 9 , wherein each map rendering mode includes the three following map operation modes: an arbitrary defect selection operation mode in which an arbitrary defect on the map is selected, an arbitrary area selection operation mode in which a defect in an arbitrary area on the map is selected, and an arbitrary area enlargement/reduction operation mode in which an arbitrary area on the map is enlarged or reduced in size.